公开(公告)号：DE1191417B

公开(公告)日：1965-04-22

申请号：DEJ0019197

申请日：1960-12-16

Applicant: IBM

Inventor： HAIBT LUTHER HAROLD ,  RABIN MICHAEL OSER

IPC: G06F11/20 ,  G11C11/44

Abstract: 902,068. Electric selective signalling systems. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 29, 1960 [Dec. 30, 1959], No. 44561/60. Class 40 (1). A signalling system is characterized in that if a fault is detected in any transmission line one of a plurality of spare lines is automatically switched into circuit to replace the faulty line. A digital system is described in which each bit of data is transmitted by sending a current along one of a pair of lines representing 0 or 1. When current will not flow down a line, a fault is indicated and the particular line in which the fault is determined by the use of a Hamming error detecting code. In Fig. 1, four bits are transmitted from a register 10 by passing current along a selected line of each of four pairs of lines M1, M2, M3, M4. These four bits then have three checking bits K1, K2, K3 added by an encoder 12 and all seven bits, M and K, are transmitted via an isolating buffer 14, a check circuit 16 and a replacement switch to the transmission lines. If one of the transmission lines in circuit develops a fault, the buffer circuit will be unable to pass current down that line. This is detected by the check circuit which, by means of three pairs of lines 20, 22 24 indicates in which line the fault lies. This information is recoded and passed to a switch control circuit 40 together with information from a shift-register 46 indicating which of the spare lines is to be used next, and as a result the faulty line is disconnected from the check circuit and a spare line is substituted. Simultaneously, the fault will have been detected at the receiving station (Fig. 2, not shown) and a similar substitution will have been made. After each substitution, the shiftregister is advanced one step so that if a further fault develops the next spare line is used. Detailed circuits for the blocks shown in Fig. 1 are given. Conventional cryotron gating techniques are used as is illustrated by Fig. 4 which shows the register 10 and the encoder 12. The register 10 comprises four storage stages, each comprising set " 0," and set " 1 " input cryotrons, two cross-coupled cryotrons, and two output cryotrons. If a set " 1 " pulse is applied, the gate conductor of the set " 1 " input cryotron becomes resistive which switches the cross-coupled pair so that the upper gate conductor becomes super-conductive and the lower one resistive, and this results in current flowing in the " 1 " line of the M1 pair of output line. The M output lines also pass through a number of series connected control windings of cryotrons in the encoder which results in the production of three check bits K1, K2, K3 in the Hamming code.

公开(公告)号：DE2628363A1

公开(公告)日：1977-01-20

申请号：DE2628363

申请日：1976-06-24

Applicant: IBM

Inventor： HAIBT LUTHER HAROLD ,  MULLERY ALVIN PAUL

IPC: G06F9/46 ,  G06F12/00 ,  G06F13/18 ,  G06F15/173 ,  G06F9/18

Abstract: A data communication network having a plurality of nodes interconnected with a communication link, wherein each node shares given ones of its data sets in common with other nodes in the network, and each node is operative to update any shared data set, except if one of the other nodes is also seeking to update the same data set, in which case the node having the higher priority prevails. Each node has a memory which stores the node location of each shared data set and the updating priority which each node has with respect to each respective set of shared data. A node receiving competing requests for update will access this memory and, depending upon the sequence of the requests, may accept a higher priority request and refuse a lower priority request.

公开(公告)号：DE1193550B

公开(公告)日：1965-05-26

申请号：DEJ0019052

申请日：1960-11-22

Applicant: IBM

Inventor： HAIBT LUTHER HAROLD

IPC: G11C15/02

Abstract: 895,137. Transfluxor circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 2, 1960 [Nov. 27, 1959], No. 37728/60. Class 40 (9). [Also in Group XIX] A binary digit is stored in two transfluxors 10, 11, Fig. 1, by setting transfluxor 10 to the blocked state and transfluxor 11 to the unblocked state for a binary one and vice versa for a binary zero, and a comparison circuit is provided whereby the values of the stored digit and a reference digit are compared and an output is produced if the two values fail to agree. When a transfluxor is blocked, the fluxes around apertures 12 and 13 are both in the same direction as denoted by arrows 1, 2 and 3 on transfluxor 11, while the fluxes are in opposite directions as shown by the corresponding arrows on transfluxor 10 when a transfluxor is unblocked. Initially the two transfluxors are brought to the binary zero state with transfluxor 10 unblocked and transfluxor 11 blocked, as shown, by a negative erase pulse in conductor 20 from an erase amplifier 22. The digit to be stored is registered in a toggle FF and a signal is applied to the transfluxors by way of a binary one or binary zero output lead 40, 42. To write a binary one, write amplifiers 28, 51 are energized when a control pulse is applied to amplifier terminal 30 and to a terminal 36 of an AND gate 34. Positive half-select pulses are consequently applied to conductors 20 and 26 which together reverse the fluxes about apertures 12 to bring transfluxors 10 and 11 to the blocked and unblocked states respectively. For comparison purposes the reference binary digit is registered in toggle FF so that an appropriate output appears on conductor 40 or 42. When a comparison control pulse is applied to terminals 46 and 48 of AND gates 50 and 52, either a read " 1 " amplifier 54 or a read " 0 " amplifier 62 is energized depending on the toggle output. A positive and a negative pulse is passed by the energized amplifier to a conductor 58 or 65, and an interrogating flux is thereby applied first in one sense and then in the opposite restoring sense about the smaller aperture 13 of the associated transfluxor. If this transfluxor is blocked, no change of magnetisation about its apertures occurs. If, however, the transfluxor is unblocked, the interrogating flux about its aperture 13 will induce output pulses in conductor 60 to indicate lack of agreement between the transfluxor and toggle FF registrations. This output will reverse the state of a toggle 76 so that a positive potential is removed from a lead 80. The transfluxors can be read out non-destructively only if the comparison is favourable, in which case the lead 80 will have a positive potential from the toggle. For this operation a read out control pulse is applied to operate relays 64 and 72 and to open an AND gate 82. A read-out amplifier 70 then becomes energized and applies a positive and a negative pulse to conductor 60. If a binary one is stored, transfluxor 10 is in the unblocked state and flux reversals will occur about its aperture 13. Consequently, an output will be induced in conductor 65 which will pass to terminal 90. If, however, a binary zero is stored, only transfluxor 10 will be unblocked and a non-effective output induced in conductor 58. This could be detected by a terminal similar to terminal 90 if a further relay 64 is provided. A number of the two-transfluxor devices, each represented by a block MM, may be arranged to form a matrix store as shown in part in Figs. 2a and 2c, the intermediate Fig. 2b being omitted. Operation is effected as previously described, each column of cores being initially set to the binary zero state by an erase pulse generator 102 and erase amplifiers 22-1 to 22-3. A binary word is registered in toggles FFa to FFd and is written into a selected column by a write pulse generator 100 selectively energizing a column write amplifier 28-1 to 28-3 at the same time as it energizes row write amplifiers 51a to 51d by opening AND gates 34a to 34d. The binary words stored may be compared simultaneously with a reference word registered in the toggles FF by energizing AND gates 50a to 50d and 52a to 52d from a read pulse generator 104a. Column toggles 76-1 to 76-3 will respond as a result to the outputs in their respective columns, and only that toggle associated with a column which has a stored word in agreement with the registered reference word will remain in its initial state. Consequently only this column will be non-destructively read when the AND gates 82-1 to 82-3 are energized from a read-out pulse generator 108, and relays 64a to 64d and 72-1 to 72-3 are operated by read-out pulse generator 106. For further comparison operations to take place the column toggles are restored by a reset pulse generator 110.