公开(公告)号：JP2000259510A

公开(公告)日：2000-09-22

申请号：JP6654799

申请日：1999-03-12

Applicant: IBM

Inventor： SUGAWARA TAKASHI ,  KOMIYAMA HIROHIDE ,  HANAMI HIDENOBU

IPC: G06F13/36 ,  G06F13/00 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To easily analyze the fault of an information processing system by examining a transaction on a primary side bus from the connector or slot of a bus bridge circuit in the manner of no destruction. SOLUTION: A jumper 60 is arranged as a control input means for switching the operating mode of a card bus controller 42, bidirectional bypass routes 40A, 66 and 58A are arranged parallel to the controller 42, the operation of the controller 42 is enabled/disabled and the operation of the bypass route is disabled/enabled corresponding to the inactive/active state of a pass through mode signal 64 from the jumper 60. A prescribed signal on a PCI bus signal line 40A or signal on a card bus signal line 58A corresponding to the prescribed signal is outputted through the bypass route onto a card bus or PCI bus as it is. In order to examine the transaction on the PCI bus, a PCI bus analyzer or exerciser is connected to a PC card slot 44A to which the bypass route is connected.

公开(公告)号：JPH10222457A

公开(公告)日：1998-08-21

申请号：JP1577297

申请日：1997-01-29

Applicant: IBM

Inventor： KAMIJO KOICHI ,  SHO IKUO ,  HANAMI HIDENOBU

IPC: G06F13/12 ,  G06F13/14 ,  G06F13/36

Abstract: PROBLEM TO BE SOLVED: To control data transfer between buses, to mutually connect the buses and to transfer data between the buses by preserving the address of an access request destination in a self retry register and terminating a bus cycle on a secondary side PCI bus not by a target abort but by retry. SOLUTION: A PCI to PCI bridge 21 temporarily terminates the bus cycle not by target abort but by retry on the secondary side PCI bus 40 operating as a target. A secondary side PCI to ISA bridge 51 executes assertion and requests the bus cycle at subtractive timing. Thus, a transaction is transmitted to a secondary side ISA device 52 being a target and data is transferred between the master secondary side PCI device 42 and the slave secondary side ISA device 52 without fail.