公开(公告)号：BR7802682A

公开(公告)日：1978-12-19

申请号：BR7802682

申请日：1978-04-28

Applicant: IBM

Inventor： AMES R ,  TAYLOR G ,  LEININGER J ,  HARDIN D

IPC: G06F13/12 ,  G06F7/00 ,  G06F9/38 ,  G06F13/38 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177 ,  G06D3/00

Abstract: An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective microcodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.