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    4.
    发明专利
    未知

    公开(公告)号：DE1222533B

    公开(公告)日：1966-08-11

    申请号：DEJ0026931

    申请日：1964-11-20

    Applicant: IBM

    Inventor： HELLERMAN HERBERT ,  IVERSON KENNETH EUGENE

    IPC: G06F13/22 ,  H04J3/16 ,  H04L5/22 ,  H04L25/06

    Abstract: 1,017,879. Multiplexing systems. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 27, 1964 [Nov. 29, 1963], No. 43684/64. Heading G4A. A system for multiplexing data from a plurality of input devices on to a common output channel includes a timing circuit associated with each device to indicate the number of sampling intervals which remain before new data will be supplied from that device, and a selection circuit adapted to output during a sampling interval the data from the device with the (or a) smallest associated said number. Application to supplying data to a computer is mentioned. Input devices 1, 2, 3, 4 (Fig. 1, not shown) supply parallel words to respective one-word buffer stores every 3, 4, 5, 5 Á secs. respectively. Each input device, when it supplies a word, also sends a " ready " signal. Figs. 2a, 2b (not shown) show a control circuit which produces, every Á sec., one or none of four " select " signals to gate the contents of a corresponding one of the buffer stores to a common output cable. The control circuit is controlled by a ring counter which cycles once every Á sec. Each " ready " signal sets a corresponding " ready " flip-flop 61, 62, 63, 64 (Fig. 2a, not shown). In the zeroth of five phases of each cycle of the ring counter, the set state of any " ready " flip-flop results in the setting to 3, 4, 5, 5 respectively of a corresponding binary clock counter and the setting of both a corresponding " available " flip-flop and a corresponding " sample " flip-flop. The " ready " flip-flops are reset during the first phase of the ring counter cycle. During the first, second and third phases those clock counters with ONES in their 4, 2 and 1 stages respectively, reset their corresponding "sample" flip-flops (provided the corresponding " available " flip-flop is still set-see below). As soon as all the " sample " flip-flops have been reset, an inverter 186 (Fig. 2b, not shown, bottom) sets again that or those " sample " flip-flops last reset. During the fourth phase of the ring counter cycle, a " select " signal is produced from the one of four AND gates 211, 212, 213, 214 (Fig. 2b, not shown) corresponding to the lowest numbered " sample " flip-flop still set (if any). This " sample " signal, besides gating the word in the corresponding buffer store to the output cable, also resets the corresponding " available " flip-flop so that the data in the buffer store cannot be gated to the output cable twice. During the zeroth phase of the next ring counter cycle, the clock counters are all decremented by one, and the above procedure repeats, and so on.

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