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    1.
    发明专利
    未知

    公开(公告)号：DE1774741A1

    公开(公告)日：1971-11-04

    申请号：DE1774741

    申请日：1968-08-24

    Applicant: IBM

    Inventor： EDWARD GARDNER PETER ALAN ,  HENRY HALLETT MICHAEL ,  JAMES TITMAN PETER

    IPC: G11C15/04 ,  H03K3/29 ,  G11C11/40

    Abstract: 1,127,270. Electric digital data storage. INTERNATIONAL BUSINESS MACHINES CORP. 5 Sept., 1967, No. 40623/67. Heading G4C. [Also in Division H3] A transistor binary storage cell, suitable for an associative store, provides the same first output signal whether it is in its " 1 " state and is interrogated for a "1" or is in its " 0 " state and is interrogated for a " 0 " and has a third state which also provides the first output signal whether it is interrogated for a " 0 " or " 1 ". The cell may have a fourth state which provides a different output signal when so interrogated. The storage cell in Fig. 4 comprises two bi-stable circuits arranged such that in state " 1 " T1 and T2 conduct, state " 0 " T1 and T3 conduct, state " 3 " T2 and T3 conduct and state " 4 " T1 and T4 conduct. Non - destructive interrogation for a " 0 " (i.e. a " 0 " match) is effected by switching the " 0 bit " a line 44 to - 0-2 V at switch 46 and the " 1 bit " line 45 to 0À1 V at switch 47. If the cell is in the " 0 " state transistor T1 is conducting but its emitter current is directed by the operation of switch 46 to emitter E12. T4 is non-conductive so that no current flows to the output line 43 from either transistor, indicating a " 0 " match. If however the circuit is in the " 1 " state the current from T4 is directed to the output line 43 indicating " no match ". Interrogating for a " 1 " match may be similarly effected and produces no current in line 43 if the match conditions exist. If the cell is in the third state neither transistor T1 nor T4 is conducting and no current flows to line 43, indicating "match" whether interrogation is for a " 0 " or a " 1 ". If however it is in the fourth state T1 and T4 both conduct and one or other current is directed to the output line 43 whether interrogation is for a " 0 " or " 1 ", indicating no match. Non-destructive read out may alternatively be effected by closing switch 49 on 0À1 V and switches 46 and 47 on 0 V. Current flowing from T1 or T4 into one or other of the bit lines 44 and 45 indicates the state of the circuit. Writing is effected by applying the interrogating voltage, such as from switches 46 and or/47, to the bit lines and lowering the threshold of the bi-stable circuits by closing switch 48 on the 2.0 V terminal and switch 49 on the 0À1 V terminal so that the transistors are into the conducting or non conducting states corresponding to the positions of switches 46 and 47. The previous state of the cell may first be destroyed by momentarily closing switch 48 on the floating terminal. If switch 49 is moved to the - 0À2 V terminal the data cell is isolated since the bit lines are then ineffective to direct the emitter currents to the output line 43. In Fig. 6 emitter followers are used in the cross couplings (as described with reference to Fig. 5, not shown) to avoid the necessity of hard saturation. In addition switch 48 is replaced by a switch 61 and the collectors of the emitter followers are taken to a tap on the collector resistors of the main transistors T1, T2, T3, T4. Interrogating and writing is carried out in a similar manner to Fig. 4 except that the lowering of the threshold to permit writing is effected by operating switch 61 to - V so as to increase the current through the emitter resistors and reduce the current through resistors R3b and R6b. Fig. 6 shows a circuit having only the first, second and third stable states, the states being represented by one of the main transistors T7, T8 or T9 conducting. These three transistors derive their input through respective emitter followers from the joint output of the other two main transistors so that any one of the main transistors will conduct only when the other two are non-conducting. Interrogating for a " 0 " is effected by placing such voltages on the bit lines 71 and 72 that if current is flowing in transistor T7 it is steered through emitter E71 to the " 0 " bit line to indicate match whereas if current is flowing in transistor T8 it is directed through emitter E82 to the word emitter line 73 to indicate no match. Interrogating for a " 1 " is similarly effected. If the circuit is in the third state (T9 conductive) no significant current reaches the output emitter lines 73 whichever interrogation is carried out and a match signal is indicated. A null interrogation is effected by placing such voltages on the bit lines that no significant current reaches the word emitter line even if T7 or T8 is conducting. Reading is effected by placing such a voltage on the word emitter line 73 that if current is flowing in transistors T7 or T8 it is diverted to the associated bit line to indicate the state of the cell. If T9 is conducting no current will appear on either line. Writing is effected by placing such a voltage on the word emitter line 73 that the switching threshold of transistors T7 and T8 is lowered and placing voltages on the bit lines 44, 45 such as to force the transistors T7 and T8 into the required conducting conditions. The cell is described in relation to an associative store (Fig. 1, not shown) in which the input register (11) is coupled to the columns of the store through a masking register (13). The cell enables one particular data position to be ignored without masking the whole of the column.

    3.
    发明专利
    未知

    公开(公告)号：DE1774606B1

    公开(公告)日：1972-04-27

    申请号：DE1774606

    申请日：1968-07-26

    Applicant: IBM

    Inventor： EDWARD GARDNER PETER ALAN ,  HENRY HALLETT MICHAEL

    IPC: G06F7/50 ,  G06F7/505 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  G11C19/28 ,  G06F7/48

    Abstract: 1,128,576. Electric digital calculators. INTERNATIONAL BUSINESS MACHINES CORP. 29 July, 1967, No. 34961/67. Heading G4A. In a multi-word data store capable of performing logical operations, bit conductors are each connected in common to the bit storage devices occupying corresponding bit positions in each of the word locations, and a plurality of majority logic gates each connect a different pair of adjacent bit conductors and produce a signal on one of the pair when the signal level on the other of the pair exceeds a threshold. Correspondingly - positioned bits of two words read simultaneously from respective rows of a matrix store are added on the column read-write lines. If the sum on a given column line exceeds 1, a threshold (majority logic) gate respective to the column adds 1 to the adjacent column line. In this way carries can be propagated during addition of two words (with end-around-carry in the case of twos-complement subtraction). After carry propagation, the sum (or difference) of the two words is obtained by a level discriminator circuit which in the case of each column line, produces a 1 output if the signal on the line is 1 or 3. Fig. 3 shows two words of the store utilizing cross-coupled pairs 6 of two-emitter transistors, each threshold gate being a transistor longtailed pair 7. The sum may be obtained, after carry propagation as above, without use of the level discriminator circuit, by a sequence of complementings, storings, majority operations (using the threshold gates and reading out three words simultaneously in each case) and shift (using an external shift register), which is described.

    6.
    发明专利
    未知

    公开(公告)号：DE1931966A1

    公开(公告)日：1970-03-05

    申请号：DE1931966

    申请日：1969-06-24

    Applicant: IBM

    Inventor： EDWARD GARDNER PETER ALAN ,  JAMES TITMAN PETER ,  HENRY HALLETT MICHAEL ,  JAMES LLEWELYN ROGER

    IPC: G06F9/26 ,  G06F9/28 ,  G11C15/04 ,  G06F13/06

    Abstract: 1,218,406. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 4 July, 1968, No. 32075/68. Heading G4A. An electronic data processing system includes two associative stores, data from one being used for an associative search in the other. General.-The system of Fig. 2 has three associative stores 21, 22, 23 each stored word having the fields shown. The local store 23 contains macro-instructions and operands, the working store 22 contains tables and the control store 21 contains sequences of micro-instructions for executing respective macro-instructions. In each store, matching may be done on the complete words or on portions indicated by the " mask " lines, and data read from or written into whole words or the portions not indicated by the respective mask lines. A match can set selectively a primary or a secondary trigger associated with the matched word, or a primary or secondary trigger associated with the next word. Reading and writing occurs with respect to that word or words having selectively either the primary trigger set or ther secondary trigger set, and if there is more than one such word the same data will be written into all such words (on writing) or the data read from the various words (on reading) will be ORed together. The set state of a primary or secondary trigger may be moved to the next such trigger for the same store, by a " next " operation. Each storage cell has three possible states 0, 1, X, the last being a " don't care " state which will match on either 0 or 1 indifferently. The macro-instructions are stored in consecutive locations in the local store, the first having a predetermined L.S. TAG field, successive macro-instructions being obtained by use of the " next " operation to step the set state of a primary trigger to the next primary trigger. The DATA 1 field of the macroinstruction is matched against the C.S. TAG fields of the control store to obtain the first micro-instruction, further micro-instructions being obtained by use of the " next " operation on the primary triggers of the store, similar to above. The L.S. TAG field of a micro-instruction can be matched against the L.S. TAG fields of the local store to obtain operands which are matched against the DATA 0 fields of the working store as the W.S. TAG of the microinstruction is matched against the W.S. TAG fields of the working store. The W.S. TAG applied specifies a stored table and the operands specify a word (or the first of a plurality of consecutive words) therein which contain the result of an operation on the operands (table look-up). The result can be transferred to the local store. The W.S. and L.S. TAGS matched against the working and local stores also control operation of the respective stores, and the control store is controlled by the C.S. OP field from itself. Micro-instruction subroutines can be sequenced through using the secondary triggers of the control store without disturbing the primary triggers used for sequencing through the main microprogramme in which the subroutine is embedded. Specifications 1,127,270 and 1,186,703 are referred to for the associative stores. Further details of table look-up.-Fig. 3 shows part of the working store for performing the AND, OR and EXCL-OR of two 4-bit operands A, B. The operands and a tag (which is 01, 11, 10 for AND, OR, EXCL-OR respectively) are matched against the corresponding " argument " fields shown in each word (row) the " output " fields of matching rows (there will be only one for AND, two for EXCL-OR and three for OR) being read out and ORed together. Shift and addition by table look-up are mentioned. Branch.-Micro-instruction branch is performed by obtaining the next micro-instruction by matching a 4-bit COND field from the working store and the C.S. TAG from the current micro-instruction (modified by ORing with the DATA 1 field from the working store, which will, however, usually be all zeros, or by the DATA 1 field from the local store) against the COND and C.S. TAG fields of the control store. The COND field from the working store indicates machine conditions, e.g. which of two operands is the larger, or overflow during addition. Macro-instruction branch is done similarly (in the local store) except that no COND field is involved. Modifications.-A conventional core store can be provided for holding the macro-instructions, its data input/output and address register both communicating with buses 27, 28 of Fig. 2. The core store is controlled by the W.S. TAGs from the control store (bus 24). An error (e.g. in an address) causes the core store to emit a C.S. TAG on bus 28 to cause entry into a diagnostic routine (no details). The local store holds instruction counts (for obtaining the next macro-instruction from the core store) which can be indexed by +1, +2, or -1 obtained from the working store, the indexing being by table look-up in the working store. The control store may be partly non-associative. Combination with second system.-The above system may be used as an interface between a transmission line and a larger data processing system, data from the line being buffered in the working store, then checked and edited before transfer to the larger system.

    8.
    发明专利
    未知

    公开(公告)号：DE1524900A1

    公开(公告)日：1970-11-26

    申请号：DE1524900

    申请日：1967-12-28

    Applicant: IBM

    Inventor： EDWARD GARDNER PETER ALAN ,  HENRY HALLETT MICHAEL

    IPC: G11C11/411 ,  G11C15/04 ,  G11C19/28 ,  H03K3/012 ,  H03K3/037 ,  H03K3/288

    Abstract: 1,162,109. Electric digital data storage. INTERNATIONAL BUSINESS MACHINES CORP. 22 Dec., 1966, No. 57536/66. Heading G4C. [Also in Division H3] A data store incorporates transistor bi-stable circuits of the type in which the collector and base electrodes of two transistors are crosscoupled and the circuits use transistors having two emitter electrodes or equivalent assemblies of transistors, the current in the conducting transistor normally passing through one emitter 6 or 7, designated the control emitter, so that the state of the circuit may be ascertained by diverting the current to the other emitter (7 or 9) designated the output emitter. Thus, by raising the potential of a control emitter, current, if flowing to the transistor, is diverted to the associated output emitter and may be detected in a sense circuit connected thereto (not shown). Writing may be effected by simultaneously raising the potential of a control emitter so as to divert the current to the output emitter and lowering the potential of the output emitter of the transistor so that it conducts. At the same time the potential of the other output emitter may be raised. Writing may alternatively be effected by applying to a control emitter a pulse that first goes negative and then positive (Fig. 3, not shown). The negative portion causes the corresponding transistor to conduct and the positive portion temporarily diverts the current to the output emitter without changing the state unless a positive pulse is also applied to the associated output emitter. The circuit is made more sensitive to writing if the potential of the supply line is simultaneously lowered or removed. The bi-stable circuits are arranged in a matrix as shown in Fig. 6, the control emitters being connected to word lines 7 and 9 and the output emitters being connected to sense column lines 6 and 8. In a contents addressable store, matching may be effected by applying the address to the word lines or alternatively by applying the complement of the address to the sense lines. Data may be transferred from one position to another in the same column. For example, a " 1 " from A 1 is transferred in inverse sense by applying a read pulse to the A 1 word line 7 to provide a write pulse in the sense line 8 which will write a " 0 " into B 1 or C 1 according to which is sensitized by lowering its supply voltage. Data may also be shifted to the right or left. Thus if a read-out pulse is applied to the upper line 7, the state of A 2 would be indicated on sense line 8. If simultaneously the lower line 7 is energized to re-set C 1 to " 0 " and gate 10 is opened, C 1 will receive the data from A 2 . Transfer to the left or right may be effected if gate 10 is as shown in Fig. 7. A data pulse being transferred causes transistor 15 to conduct, cutting off 16 and whichever of 11 or 12 was previously rendered conducting by left or right shift control signals. The rise of collector voltage at the corresponding collector provides the write pulse. Logic transfer of data may alternatively be effected. Thus if A 1 andB 1 are read out simultaneously into sense line 8 and C 1 is sensitized by lowering its collector supply voltage, then C 1 will be changed to the " 1 " state if A 1 and B 1 were both " 0." Alternatively if A 1 and B 1 are read out into sense line 6 and C 1 sensitized then a " 1 " will be written into C 1 if A 1 or B 1 is "0." Again, if A 1 and B 1 are opposite and are read into sense lines 6 and 8 simultaneously then C 1 if sensitized will become " 0 " if both are " 0 " and " 1 " if both are 1." If the sense bias lines 6 are connected diagonally instead of vertically then diagonal shifting may be effected without external gating (Fig. 8, not shown). In this case the complement is shifted.

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