公开(公告)号：CA2099413A1

公开(公告)日：1994-05-01

申请号：CA2099413

申请日：1993-06-30

Applicant: IBM

Inventor： HARDELL WILLIAM R JR ,  HENSON JAMES D JR ,  MITCHELL OSCAR R

IPC: G06F1/00 ,  G06F9/445 ,  G06F15/167 ,  G06F15/173 ,  G06F15/80 ,  G06F1/12

Abstract: An architecture and method for booting a multi-processor system having processor local memory and shared global memory, with shared global memory access managed by an atomic memory access controller and cache coherence managed by software. Reset circuits are used to synchronize to a master clock a commonly distributed start signal and processor individualized restart sequences, which reset circuit signals are distributed to reset both local and global memory. Global memory testing is assigned to a processor based upon its rate status in completing an internal test sequence. The systems and methods are particularly suited to booting a group of multiple but relatively independent processors. Furthermore, the practice of the invention facilitates booting of such system when one or more of the processors have been disconnected or failed.