公开(公告)号：FR2375717A1

公开(公告)日：1978-07-21

申请号：FR7727691

申请日：1977-09-09

Applicant: IBM

Inventor： CORBIN VIVIAN R ,  HITCHNER JAMES E ,  PATNAIK BISWESWAR ,  TING CHUNG-YU

IPC: H05K3/46 ,  H01L21/28 ,  H01L21/306 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L21/82

Abstract: A method for forming self-aligned via holes which are used to interconnect levels of thin films atop substrates. A first level thin film pattern, typically comprising raised metallic stripes, is formed atop the substrate. A first level dielectric material is then deposited in blanket fashion so that the topology of the insulator conforms to the topology of the pattern. Next, a material such as polymer is deposited which tends to form a planar surface, with a greater thickness of polymer accumulating between the protuberances of the insulator than atop said protuberances. A mask is then applied, exposed and developed at selected regions where via holes are to be formed in the dielectric. A small amount of the polymer is etched, preferably in a plasma, to expose the insulator. Then the latter is etched to form the via holes. Accurately located via holes are formed, even if the mask is misaligned.