公开(公告)号：WO2010012633A3

公开(公告)日：2010-06-24

申请号：PCT/EP2009059395

申请日：2009-07-22

Applicant: IBM ,  IBM UK ,  BENDER CARL ALFRED ,  HOCHSCHILD PETER HEINER ,  MISRA ASHUTOSH ,  SWETZ RICHARD

Inventor： BENDER CARL ALFRED ,  HOCHSCHILD PETER HEINER ,  MISRA ASHUTOSH ,  SWETZ RICHARD

IPC: G06F11/34

CPC classification number: H03K21/00 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  H03K23/42

Abstract: There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated "pre-counter" while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the "sweeper" state machine accesses the pre-counter.

Abstract translation: 这里广泛地考虑了一种安排，其中每个事件源提供一个小的专用“预计数器”，而实际的计数保存在64位宽的RAM中。 这样的实施方式优选地可以包括以预定的固定顺序简单地扫过预计数器的状态机。 优选地，状态机将访问每个预计数器，将来自预计数器的值添加到相应的RAM位置，然后清除预计数器。 因此，预计数器只需要足够宽，使得即使在最大事件速率下，在“清扫器”状态机访问预先计数器之前，预计数器将不能够包装（即达到容量或溢出） 计数器。

公开(公告)号：GB2357412B

公开(公告)日：2003-12-10

申请号：GB0019066

申请日：2000-08-04

Applicant: IBM

Inventor： DENNEAU MONTY MONTAGUE ,  HOCHSCHILD PETER HEINER ,  WARREN JR HENRY STANLEY

IPC: G06T1/20

Abstract: The geometric processing of an ordered sequence of graphics commands is distributed over a set of processors by the following steps. The sequence of graphics commands is partitioned into an ordered set of N subsequences S0 . . . SN-1, and an ordered set of N state vectors V0 . . . VN-1 is associated with said ordered set of subsequences S0 . . . SN-1. A first phase of processing is performed on the set of processors whereby, for each given subsequence Sj in the set of subsequences S0 . . . SN-2, state vector Vj+1 is updated to represent state as if the graphics commands in subsequence Sj had been executed in sequential order. A second phase of the processing is performed whereby the components of each given state vector Vk in the set of state vectors V1 . . . VN-1 generated in the first phase is merged with corresponding components in the preceding state vectors V0 . . . Vk-1 such that the state vector Vk represents state as if the graphics commands in subsequences S0 . . . Sk-1 had been executed in sequential order. Finally, a third phase of processing is performed on the set of processors whereby, for each subsequence Sm in the set of subsequences S1 . . . SN-1, geometry operations for subsequence Sm are performed using the state vector Vm generated in the second phase. In addition, in the third phase, geometry operations for subsequence S0 are performed using the state vector V0. Advantageously, the present invention provides a mechanism that allows a large number of processors to work in parallel on the geometry operations of the three-dimensional rendering pipeline. Moreover, this high degree of parallelism is achieved with very little synchronization (one processor waiting from another) required, which results in increased performance over prior art graphics processing techniques.

公开(公告)号：GB2357412A

公开(公告)日：2001-06-20

申请号：GB0019066

申请日：2000-08-04

Applicant: IBM

Inventor： DENNEAU MONTY MONTAGUE ,  HOCHSCHILD PETER HEINER ,  WARREN JR HENRY STANLEY

IPC: G06T1/20

Abstract: The geometric processing of an ordered sequence of graphics commands is distributed over a set of processors by the following steps. The sequence of graphics commands is partitioned into an ordered set of N subsequences S 0 .. S N-1 , and an ordered set of N state vectors V 0 .. V N-1 is associated with said ordered set of subsequences S 0 .. S N-1 . A first phase of processing is performed on the set of processors whereby, for each given subsequence S j in the set of subsequences S 0 .. S N-2 , state vector V j+1 is updated to represent state as if the graphics commands in subsequence S j had been executed in sequential order. A second phase of the processing is performed whereby the components of each given state vector V k in the set of state vectors V 1 .. V N-1 generated in the first phase is merged with corresponding components in the preceding state vectors V 0 .. V k-1 such that the state vector V k represents state as if the graphics commands in subsequences S 0 .. S k-1 had been executed in sequential order. Finally, a third phase of processing is performed on the set of processors whereby, for each subsequence S m in the set of subsequences S 1 .. S N-1 , geometry operations for subsequence S m are performed using the state vector V m generated in the second phase. In addition, in the third phase, geometry operations for subsequence S 0 are performed using the state vector V 0 . Advantageously, the present invention provides a mechanism that allows a large number of processors to work in parallel on the geometry operations of the three-dimensional rendering pipeline. Moreover, this high degree of parallelism is achieved with very little synchronization (one processor waiting from another) required, which results in increased performance over prior art graphics processing techniques.