公开(公告)号：WO02056340A3

公开(公告)日：2003-06-26

申请号：PCT/GB0105716

申请日：2001-12-21

Applicant: IBM ,  IBM UK

Inventor： CABRAL CYRIL ,  CLEVENGER LAWRENCE ,  HSU LOUIS LU-CHEN ,  WONG KEITH KWONG HON

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/525 ,  H01L27/06 ,  H01L23/64

CPC classification number: H01L21/76849 ,  H01L21/7687 ,  H01L21/76888 ,  H01L23/5258 ,  H01L27/0629 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes at least one fuse, resistor, diffusion barrier or capacitor that is formed of refractory metal-silicon-nitrogen. A suitable refractory material is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N.

Abstract translation: 半导体结构包括由难熔金属硅 - 氮形成的至少一个熔丝，电阻器，扩散阻挡层或电容器。 合适的耐火材料是TaSiN，其通过改变Ta:Si:N的比例来提供宽范围的电阻率。

公开(公告)号：WO0231867A3

公开(公告)日：2002-10-17

申请号：PCT/GB0104430

申请日：2001-10-05

Applicant: IBM ,  IBM UK

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE ,  HSU LOUIS LU-CHEN ,  WONG KWONG HON

IPC: H01L21/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0688

Abstract: Electronic structure that has in-situ formed resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The structure may be combined with a capacitor network to form RC circuits.

Abstract translation: 具有原位形成的电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件，形成在顶部上并与第一多个导电元件中的至少一个电连通的多个电阻通孔，以及 形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。 该结构还可以形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。 该结构可以与电容器网络组合以形成RC电路。

公开(公告)号：JPH11317523A

公开(公告)日：1999-11-16

申请号：JP505799

申请日：1999-01-12

Applicant: IBM

Inventor： HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To obtain a device, which has active devices formed on roughly continuous mesa regions, which are formed on more than one surfaces of an isolation region and consist of a semiconductor material, and conductive paths, which are formed on the mesa regions and are extended in the lengthwise directions of the mesa regions. SOLUTION: A semiconductor device has first active devices formed on mesa regions, which are formed by more than one sidewall of an isolation region 15 and consist of a semiconductor material, and conductive paths. The conductive paths are extended from the active devices to the lengthwise directions of the mesa regions. In one embodiment, a plurality of active devices are respectively formed on mesa region, and the active devices are connected electrically with each other through the mesa regions.

公开(公告)号：WO2007051765A3

公开(公告)日：2007-06-28

申请号：PCT/EP2006067883

申请日：2006-10-27

Applicant: IBM ,  IBM UK ,  HSU LOUIS LU-CHEN ,  MANDELMAN JACK ,  TONTI WILLIAM

Inventor： HSU LOUIS LU-CHEN ,  MANDELMAN JACK ,  TONTI WILLIAM

IPC: H01L23/525

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrically programmable fuse (eFuse) includes (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. The diode comprises an N+,p-,P+ or P+,n-,N+ structure.

Abstract translation: 电可编程熔丝（eFuse）包括（1）衬底的绝缘氧化物层上的半导体层; （2）形成在半导体层中的二极管; 和（3）在二极管上形成的硅化物层。 二极管包括N +，p-，P +或P +，n-，N +结构。

公开(公告)号：WO02095586A3

公开(公告)日：2003-10-16

申请号：PCT/GB0202302

申请日：2002-05-15

Applicant: IBM ,  IBM UK

Inventor： CHEN HOWARD HAO ,  HSU LOUIS LU-CHEN ,  WANG LI-KONG

IPC: G01R31/28 ,  G06F11/22 ,  G06F11/27 ,  H01L21/822 ,  H01L27/04 ,  G01R31/3187

CPC classification number: G06F11/27

Abstract: Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.

Abstract translation: 分层内置的自检方法和安排来验证系统功能。 因此，提供了一种有效的内置自检方法，用于进行完整的片上系统测试，以确保系统级芯片设计的电路可靠性和性能。 作为一个额外的优势，系统级芯片应用程序的开发成本有所降低。

公开(公告)号：WO0229818A3

公开(公告)日：2003-06-19

申请号：PCT/EP0110937

申请日：2001-09-21

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： HSU LOUIS LU-CHEN ,  PARENT RICHARD MICHAEL ,  WORDEMAN MATTHEW R

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/406 ,  G11C5/146 ,  G11C8/08 ,  G11C11/4074 ,  G11C2207/104

Abstract: A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.

Abstract translation: 用于实现Vbb（阵列体偏置）和Vwl（负字线）电压发生器的存储电路中的功耗的显着降低的系统和方法。 该系统包括在睡眠或待机模式期间关闭负WL发生器，使得不消耗电力。 执行松弛的刷新操作，负的WL由Vbb发生器供电。 由于联合Vbb-Vwl去耦方案，耦合到BL摆幅的负WL电源的噪声减小。 在活动模式下，Vbb和Vneg被分离，以避免任何交叉噪声并保持设计灵活性。 在上电期间，Vwl发生器提高了Vbb电平的上升速率。 其优点可概括为：（1）Vbb发电机设计更简单，（2）Vbb发电机尺寸小得多，（3）Vbb功率降低，（4）Vwl发电机无待机电流，（5）低去耦噪声 待机或休眠模式下的Vwl电平，（6）上电时Vbb的提升速率，（7）活动模式期间Vbb和Vwl之间无交叉噪声，（8）Vbb和Vbb的设计灵活性 Vwl处于活动模式。 本发明的原理和优点可以应用于任何两个或多个DC发电机系统，负极或正极。

公开(公告)号：JP2007227921A

公开(公告)日：2007-09-06

申请号：JP2007037720

申请日：2007-02-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN ,  YANG CHIH-CHAO

IPC: H01L21/3205 ,  H01L21/312 ,  H01L21/316

CPC classification number: H01L21/31695 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31633 ,  H01L21/7682 ,  H01L21/76831

Abstract: PROBLEM TO BE SOLVED: To provide a dielectric having a reduced dielectric constant, and to provide its manufacturing method.
SOLUTION: In a first embodiment, a first method of manufacturing a dielectric having a reduced dielectric constant is provided. The first method includes the steps of: (1) forming a dielectric layer including a trench on a substrate; and (2) forming a cladding region in the dielectric layer by forming a plurality of air gaps in the dielectric layer along at least one of a sidewall and a bottom of the trench so as to reduce an effective dielectric constant of the dielectric. Numerous other aspects are provided.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有降低的介电常数的电介质，并提供其制造方法。 解决方案：在第一实施例中，提供了制造具有降低的介电常数的电介质的第一种方法。 第一种方法包括以下步骤：（1）在衬底上形成包括沟槽的电介质层; 以及（2）通过沿着沟槽的侧壁和底部中的至少一个在电介质层中形成多个空气间隙来形成电介质层中的包层区域，以便降低电介质的有效介电常数。 提供了许多其他方面。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007123881A

公开(公告)日：2007-05-17

申请号：JP2006286995

申请日：2006-10-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： XU HUIHAO ,  CAMARA HIBOURAHIMA ,  KARL D SELANDER ,  STEVEN J ZIER ,  HSU LOUIS LU-CHEN ,  ROCKROHR JAMES D

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H03K17/08 ,  H03K17/693 ,  H03K19/003

CPC classification number: H03K17/223 ,  G05F3/262 ,  G11C5/144 ,  G11C5/145 ,  G11C7/20 ,  H03K17/08

Abstract: PROBLEM TO BE SOLVED: To provide a system for protecting a weak device operated in a micro-electronic circuit inclusive of a high voltage electric power supply from excess stress caused by a high voltage.
SOLUTION: This system prevents a weak device from failing during an increase in output, during a decrease in output, and when a low voltage electric power supply is absent in a multiple electric power supply system. This system is provided with a circuit for detecting a low-voltage electric power supply configured to detect an increase in output of a circuit, a decrease in output of a circuit, and when a low-voltage electric power supply is absent and generate a control signal after the detection. This system further has a controllable current mirror device configured to supply a trickle current during an increase in output of a circuit, during a decrease in output of a circuit, and when a low-voltage electric power supply is absent, in response to a control signal received from the circuit for detecting a low-voltage electric power supply, to maintain a conductive channel of the weak device.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于保护在包括高压电源的微电子电路中操作的弱电装置免受由高电压引起的过度应力的系统。 解决方案：该系统防止在输出增加，输出减少期间以及在多电力供应系统中不存在低压电力供应时，弱装置发生故障。 该系统设置有用于检测被配置为检测电路的输出增加，电路的输出的减少以及当没有低电压电源时产生控制的低电压电源的电路 检测后信号。 该系统还具有可控电流镜装置，其被配置为在电路的输出增加期间在电路的输出减小期间提供涓流电流，并且当低电压电源不存在时，响应于控制 从用于检测低压电源的电路接收的信号，以维持弱装置的导电通道。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007273988A

公开(公告)日：2007-10-18

申请号：JP2007086288

申请日：2007-03-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WONG KEITH KWONG HON ,  ARNOLD JOHN CHRISTOPHER ,  GAIDIS MICHAEL CHRISTOPHER ,  RADENS CARL JOHN ,  YANG CHIH-CHAO ,  HSU LOUIS LU-CHEN ,  DALTON TIMOTHY JOSEPH ,  CLEVENGER LAWRENCE A

IPC: H01L27/105 ,  H01L45/00

CPC classification number: H01L45/1675 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: PROBLEM TO BE SOLVED: To provide a phase change memory element connected to the edge part of a thin film electrode, and to provide a method of manufacturing the same.
SOLUTION: A phase change memory (PCM) cell structure includes a first electrode 60E, a phase change element 70E, and a second electrode 80E, wherein the phase change element 70E is inserted between the first electrode 60E and the second electrode 80E, and only an edge part 75 of the first electrode 60E is contacted with the phase change element 70E, thereby reducing a contact area between the phase change element 70E and the first electrode 60E to increase a current density flowing through the phase change element 70E and effectively cause a phase change by a first programming power by a comparatively small current.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供连接到薄膜电极的边缘部分的相变存储元件，并提供其制造方法。 解决方案：相变存储器（PCM）单元结构包括第一电极60E，相变元件70E和第二电极80E，其中相变元件70E插入在第一电极60E和第二电极80E之间 并且只有第一电极60E的边缘部分75与相变元件70E接触，从而减小相变元件70E和第一电极60E之间的接触面积，以增加流过相变元件70E的电流密度和 通过相对小的电流有效地引起第一编程功率的相位变化。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2004212387A

公开(公告)日：2004-07-29

申请号：JP2003413983

申请日：2003-12-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN HOWARD H ,  HSU LOUIS LU-CHEN ,  JI BRIAN L ,  WANG LI-KONG

IPC: G01R31/00 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  G06F15/00 ,  G11C29/00 ,  G11C29/12 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04

CPC classification number: G01R31/3004 ,  G01R31/31721

Abstract: PROBLEM TO BE SOLVED: To provide a device for monitoring hierarchical power source noise and a system for VLSI (very large scale integration) circuits.
SOLUTION: In the system for monitoring hierarchical power source noise, the noise monitoring device is manufactured on-chip, and the noise on a chip is measured. In the noise-monitoring system, the plurality of on-chip noise-monitoring devices are distributed effectively in the chip. A noise analysis algorithm analyzes a noise characteristic, based on a collected noise data from the noise monitoring device, and the hierarchical noise monitoring system performs mapping operation to the system on the chip for the noise of each core.
COPYRIGHT: (C)2004,JPO&NCIPI