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    ADAPTIVE ASYNCHRONOUS EQUALIZATION USING LEAKAGE
    1.
    发明申请
    ADAPTIVE ASYNCHRONOUS EQUALIZATION USING LEAKAGE 审中-公开
    使用泄漏的自适应异步均衡

    公开(公告)号：WO2007051693A3

    公开(公告)日：2007-06-28

    申请号：PCT/EP2006067340

    申请日：2006-10-12

    Applicant: IBM ,  IBM UK ,  HUTCHINS ROBERT ALLEN ,  ELEFTHERIOU EVANGELOS ,  OELCER SEDAT ,  JELITTO JENS

    Inventor： HUTCHINS ROBERT ALLEN ,  ELEFTHERIOU EVANGELOS ,  OELCER SEDAT ,  JELITTO JENS

    IPC: G11B20/10 ,  H03H21/00 ,  H04L25/03

    CPC classification number: G11B20/10009 ,  G11B20/10046 ,  G11B20/10175 ,  G11B20/10481 ,  H04L25/03019 ,  H04L2025/03484 ,  H04L2025/03681

    Abstract: An apparatus, system, and method are disclosed for adaptive asynchronous equalization using leakage. An equalizer sums products of a plurality of tap signals from a delay line sampling a read signal and a plurality of corresponding tap coefficients to form an equalized signal in an asynchronous time domain having a first sampling rate. A leaky function module calculates a leaky function for each tap coefficient in the asynchronous time domain. An adaptation module adapts each of the tap coefficients as the leaky function for each tap coefficient summed with a signal-dependent updating function for each tap coefficient.

    Abstract translation: 公开了一种使用泄漏进行自适应异步均衡的装置，系统和方法。 均衡器对来自对读取信号进行采样的延迟线和多个对应抽头系数的多个抽头信号的乘积进行求和，以在具有第一采样率的异步时域中形成均衡的信号。 泄漏功能模块计算异步时域中每个抽头系数的泄漏函数。 适配模块将每个抽头系数适配为每个抽头系数的泄漏函数，用于针对每个抽头系数的与信号相关的更新函数相加。

    SYNCHRONIZATION OF SYMMETRIC TIMING BASED SERVO BURSTS
    3.
    发明申请
    SYNCHRONIZATION OF SYMMETRIC TIMING BASED SERVO BURSTS 审中-公开
    基于对称时序的伺服脉冲同步

    公开(公告)号：WO2011104050A2

    公开(公告)日：2011-09-01

    申请号：PCT/EP2011050674

    申请日：2011-01-19

    Applicant: IBM ,  CHERUBINI GIOVANNI ,  JELITTO JENS ,  LANTZ MARK ALFRED ,  HUTCHINS ROBERT ALLEN

    Inventor： CHERUBINI GIOVANNI ,  JELITTO JENS ,  LANTZ MARK ALFRED ,  HUTCHINS ROBERT ALLEN

    CPC classification number: G11B5/584 ,  G11B5/09

    Abstract: Timing based servo bursts of servo frames, in which the frames are arranged to be symmetric with the same number of servo stripes in each burst of a frame, are synchronized by shifting selected bits. For example, servo frames are arranged with four servo bursts with an equal number of servo stripes in each burst, the servo frames comprising two symmetric sub-frames, each sub-frame comprising two bursts of servo stripes that are parallel to each other within a burst, and the bursts are non-parallel with respect to each other; each servo burst is arranged to comprise at least one reference servo stripe; and each servo burst is arranged to comprise at least one shifted servo stripe, wherein the shift is in the same longitudinal direction with respect to at least one reference servo stripe for each burst of a frame and the opposite longitudinal direction for bursts of sequentially adjacent frames.

    Abstract translation: 伺服帧的基于时序的伺服脉冲串通过移位所选位来同步，其中帧被布置为在帧的每个突发中具有相同数量的伺服条带对称。 例如，伺服帧被布置成具有在每个突发中具有相等数量的伺服条带的四个伺服脉冲串，伺服帧包括两个对称子帧，每个子帧包括在一个内部的彼此平行的两个脉冲串的伺服条带 突发，并且突发是相互不平行的; 每个伺服脉冲串被布置成包括至少一个参考伺服条纹; 并且每个伺服脉冲串被布置成包括至少一个移位的伺服条带，其中相对于帧的每个脉冲串相对于至少一个参考伺服条带的移位在相同的纵向方向上，并且相反的纵向方向用于顺序相邻帧的突发 。

    Error combination logic configured for multi-channel data detection system, and method for generating error signal
    6.
    发明专利
    Error combination logic configured for multi-channel data detection system, and method for generating error signal 有权
    用于多通道数据检测系统的错误组合逻辑和用于产生错误信号的方法

    公开(公告)号：JP2009095028A

    公开(公告)日：2009-04-30

    申请号：JP2008262296

    申请日：2008-10-08

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： HUTCHINS ROBERT ALLEN ,  JELITTO JENS ,  OELCER SEDAT

    IPC: H03L7/091

    Abstract: PROBLEM TO BE SOLVED: To provide phase-error combination logic for a multi-channel data detection system with a phase locked loop for each channel.
    SOLUTION: The phase-error combination logic comprises receiving phase error information with respect to each channel; combination logic configured to combine the received phase error information and generate a combined phase error; and a phase-error output configured to apply the combined phase error to at least one channel phase locked loop. Additionally, error signal combination logic comprises receiving error information of a signal relevant to a phase locked loop with respect to each channel; combination logic configured to combine the received error signal information and generate a combined error signal, weighting the received error signal information from each channel, for example with reliability information. An error compensation output is configured to apply the combined, weighted error signal to at least one channel phase locked loop.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：为具有每个通道的锁相环的多通道数据检测系统提供相位误差组合逻辑。 解决方案：相位误差组合逻辑包括接收关于每个通道的相位误差信息; 组合逻辑，被配置为组合所接收的相位误差信息并产生组合的相位误差; 以及被配置为将组合的相位误差应用于至少一个通道锁相环的相位误差输出。 另外，误差信号组合逻辑包括相对于每个信道接收与锁相环相关的信号的误差信息; 组合逻辑，其被配置为组合所接收的误差信号信息并产生组合误差信号，例如用可靠性信息对来自每个信道的接收到的误差信号信息进行加权。 误差补偿输出被配置为将组合的加权误差信号应用于至少一个通道锁相环。 版权所有（C）2009，JPO＆INPIT

    READING AND DETECTION CHANNEL AND ITS METHOD CAPABLE OF DECODING DATA STORED IN DATA RECORDING MEDIUM
    7.
    发明专利
    READING AND DETECTION CHANNEL AND ITS METHOD CAPABLE OF DECODING DATA STORED IN DATA RECORDING MEDIUM 失效

    公开(公告)号：JPH1069732A

    公开(公告)日：1998-03-10

    申请号：JP10554397

    申请日：1997-04-23

    Applicant: IBM

    Inventor： HUTCHINS ROBERT ALLEN ,  GLEN ALAN JIYAKUETSUTA ,  ALAN ROBERT CLARKE

    IPC: G11B20/14 ,  G11B7/005 ,  G11B19/12 ,  G11B20/18

    Abstract: PROBLEM TO BE SOLVED: To provide a readout-detection channel and an improved method for decoding the data stored in a data storing medium. SOLUTION: A readout-detection channel 20 includes a tracking threshold value circuit 34 which generates variable threshold value signals and a detection circuit which can be configured into a plurality of various configurations each of which corresponds to one of a plurality of various data forms. Furthermore, a first embodiment of the readout detection channel 20 includes the structural circuit which automatically selects one structure of the data detection circuit in response to detection in the form of input data stream. This first embodiment allows the data bits coded in a plurality of divergent data forms to be decoded using a singly constructible readout detection channel.

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