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公开(公告)号：JPH10106173A
公开(公告)日：1998-04-24
申请号：JP24477396
申请日：1996-09-17
Applicant: IBM
Inventor： IOKI KAZUYA
Abstract: PROBLEM TO BE SOLVED: To control phases of data windows so that data having a low data error rate can be obtained. SOLUTION: In a method reading out data from a recording medium having a data area in which clocks and data are stored, data windows for separating the data and clocks are generated based on a pulse train to be obtained from the recording medium (45). At this time, when parts in which plural bits are arranged symmetrically and which are compatible to bit patterns which do not affected by a peack shift and include reference positions are obtained from the pulse train to be obtained from the data area, phases of the data windows are controlled based on compatible parts. These bit patterns are stored in a pattern storage part 42 and they are compared with the pulse train. Thus, the correct read-out of data is made possible by separating the data and clocks from the pulse train obtained from the recording medium while using the data windows controlled in this manner.
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公开(公告)号：JP2001118378A
公开(公告)日：2001-04-27
申请号：JP29362899
申请日：1999-10-15
Applicant: IBM
Inventor： IOKI KAZUYA
Abstract: PROBLEM TO BE SOLVED: To effectively use a storage region by collecting two FIFO of FIFO for transmission and FIFO for reception into one FIFO. SOLUTION: A FIFO storage device 10 is provided with a FIFO control section 20 for transmission writing transmission input data in a memory 100 and reading out and outputting transmission data stored in a memory 100 in order of input, a FIFO control section 30 for reception writing reception input data in a memory 100 and reading out and outputting reception data stored in the memory 100 in order of input, a first pointer register 26 storing an address of the memory 100 reading out an address of the memory 100 to which transmission data is written or transmission output data, and second pointer register 36 storing an address of the memory 100 to which reception input data is written or an address of the memory 100 from which reception output data is read out.
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公开(公告)号：JPH09307407A
公开(公告)日：1997-11-28
申请号：JP11470496
申请日：1996-05-09
Applicant: IBM
Inventor： IOKI KAZUYA , NISHIHARA MICHITETSU
Abstract: PROBLEM TO BE SOLVED: To reduce consuming area, to improve the stability, to attain a high convergence speed and to avoid problems for mount and correspondence to a design change by adopting a digital circuit for a clock oscillator. SOLUTION: A delay element chain 20 is formed by connecting an array of 2-stage inverters 22 as a delay element in series. A delay element selection section 30 such as a shift register to store bits to indicate a selecting state is connected to each array of the inverters 22 as a means to select a desired array of the inverters 22. The delay element chain 20 is connected to an external clock 1 via an input logic circuit 7. A wiring 40 is used to form a proper closed loop between the selected array of the inverters 22 and the input logic circuit 7. Since number of the delay elements included in the closed loop differs depending which of the array is selected among the arrays of the inverters 22 connected in series, the oscillating frequency of the clock oscillator is changed.
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