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公开(公告)号：US3675216A
公开(公告)日：1972-07-04
申请号：US3675216D
申请日：1971-01-08
Applicant: IBM
Inventor： JAMES RANDELL L
Abstract: A shift register and control technique in which no clocking is employed between the control logic, the shift register, and the input to and output from the shift register. Upon start-up of the system a flag code is loaded at random, into a stage of the register and the remaining stages or data positions of the register are loaded with dummy code. Thereafter, the control logic and input to and output from the shift register is timewise controlled by the sensing of the flag which, in the case that the associated input and output means is a typewriter, moves synchronously with the print element or carriage of the typewriter. Four buffers which are connected to the control logic and the data buss for data input to an output from the shift register are connected between the input and output stages of the register and these buffers are logically selectively introduced into the data flow upon the sensing of the flag in the output stage of the register to accomplish timewise shifting of the data in the register for insertion of additional data, deletion of data, and other usual functions such as error correct backspace. Due to the utilization of the sensing of the flag to control the instant that a change in the data path is made no clocking between the input/output and control logic is required and additionally, the length of the shift register can be increased or decreased or the basic timing changed without any change in the control logic.
Abstract translation: 移位寄存器和控制技术，其中在控制逻辑，移位寄存器和从移位寄存器输入和输出的输入之间不采用时钟。 在系统启动时，将标志码随机加载到寄存器的一级，并且寄存器的剩余级或数据位置加载虚拟代码。 此后，控制逻辑和从移位寄存器输出并输入到时间上通过感测标志来控制，该标志在相关联的输入和输出装置是打字机的情况下与打字机的打印元件或滑架同步地移动 。 连接到控制逻辑的四个缓冲器和用于输入到移位寄存器的输出的数据总线连接在寄存器的输入和输出级之间，并且这些缓冲器在感测到数据流时被逻辑地选择性地引入到数据流中 标志在寄存器的输出级中，以完成时间上移位寄存器中的数据以插入附加数据，删除数据以及其他常规功能，如错误校正退格。 由于利用了标志的感测来控制数据路径的变化而不需要输入/输出和控制逻辑之间的时钟，另外还可以增加或减少移位寄存器的长度， 基本时序在控制逻辑中没有任何改变而改变。
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Patent Agency Ranking
公开(公告)号：CA984514A
公开(公告)日：1976-02-24
申请号：CA163174
申请日：1973-01-29
Applicant: IBM
Inventor： BLUETHMAN ROBERT G , JAMES RANDELL L
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公开(公告)号：FR2315801A1
公开(公告)日：1977-01-21
申请号：FR7614188
申请日：1976-05-06
Applicant: IBM
Inventor： JAMES RANDELL L , PADDEN JAMES T
Abstract: Disclosed is a method and apparatus for detecting the presence of signals, particularly touch-tone signals, of characteristic complex waveforms by comparing unknown signals with pre-specified digital formats or "masks" representative of such waveforms. The apparatus includes digital circuitry defining the masks and digital circuitry for counting the number of times during a prescribed time period there is a correlation between the digital format of the unknown signals and the masks.
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公开(公告)号：CA974589A
公开(公告)日：1975-09-16
申请号：CA165483
申请日：1973-02-28
Applicant: IBM
Inventor： JAMES RANDELL L
IPC: G01R31/28 , G01R31/3185 , G06F11/22 , H01L21/66 , H01L21/822 , H01L27/04
Abstract: A technique of decreasing the number of test patterns required to test a MOSFET module and/or provide the ability to test elements on the module which can not be tested by conventional test techniques. Conventionally, test patterns are applied to the input pins of a MOSFET module and the output monitored at the output pins of the module. Interwoven with the normal test pattern testing is the application of a serial test pattern to selected elements on the module. The serial test pattern is applied to a single input pin on the module and a serial test pattern is stored in a shift register which is on the module. Each of the stages of the shift register are used to control or monitor an element or point which may be otherwise inaccessible or untestable and the shift register is also utilized in an output mode to provide an indication serially on a single output pin as to the functioning of the points accessed on the module. The sequence then is to input onto a single input pin a serial test pattern for testing, controlling or monitoring various elements or nets on the module; reload the shift register in accordance with the test results; and then serially shift the contents of the shift register out onto the single output pin while monitoring this output to determine whether the elements or nets are functioning properly. In addition, while the serial test pattern is applied the output appearing at the output pins of the module may be monitored.
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公开(公告)号：CA986183A
公开(公告)日：1976-03-23
申请号：CA181280
申请日：1973-09-18
Applicant: IBM
Inventor： JAMES RANDELL L
IPC: G01R31/26 , G01R31/28 , G01R31/3185 , G01R31/319 , G06F11/22 , H01L21/66 , H01L21/822 , H01L27/04
Abstract: A technique of testing a MOSFET planar board in which each of the chips on the planar board can be electronically isolated for individual testing. In MOSFET technology there are two off chip inverters between the output logic blocks and the pins. These are the preoff chip inverter and the off chip inverter. A NOR gate is formed by adding an additional input line to each of the preoff chip inverters of each of the chips on the board, and the output of each of the chips which are not to be tested are driven to logical ones by application of a positive logical level to this input line while no input is applied to the NOR gates on the outputs of the chip which is to be tested. In this manner, all inputs to the chip to be tested are at a one or high logical level, and for test purposes each input to the chip can be brought to a low logical level or left at a high logical level in accordance with the test pattern to be applied. Its output or reaction to the input test patterns is monitored in the normal manner by the chip tester. Through utilization of this technique, the same test patterns which might number three thousand can be applied to the chip such that even though it remains on the planar board it can be tested equivalent to new. In this manner, each chip can be tested and a defective chip on a planar board isolated without mechanically isolating the chips by breaking chip interconnections.
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