公开(公告)号：JP2002252287A

公开(公告)日：2002-09-06

申请号：JP2002004213

申请日：2002-01-11

Applicant: IBM

Inventor： JASINSKI ERIC ,  KEMERER DOUGLAS W

IPC: H01L27/11 ,  G11C5/06 ,  G11C11/412 ,  H01L21/8244

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell-array in which the minimum feature size of a design rule can be sufficiently used without considerably lowering production yield. SOLUTION: An electric power junction 160 extends zigzag into an adjoining line. Other electric power junctions 170 connect the electric power junctions of memory cells of adjoining columns with adjoining lines to each other. A subarray layout can be extended by reflection. A comparatively large amount of memory cell can be formed by lithographic exposure using step and repeat method. The layout of electric power junctions for memory cells considerably decrease the number of needed electric power junctions and/or the layout makes possible to form redundant junctions and shield meshes without increasing the number of needed junctions, further the enough use of the minimum future size become possible with increased production yield.

公开(公告)号：JP2003068085A

公开(公告)日：2003-03-07

申请号：JP2002184247

申请日：2002-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CHADWICK THOMAS B ,  GORDON TARL S ,  JASINSKI ERIC ,  NADKARNI RAHUL ,  OUELLETTE MICHAEL R

IPC: G11C15/04 ,  G11C29/56 ,  G11C29/00

CPC classification number: G11C15/04

Abstract: PROBLEM TO BE SOLVED: To provide an address memory (CAM) in which the number of times of pre-charge is reduced and power consumption can be reduced securing high speed operation.
SOLUTION: A synkline and a matchline are reset to second voltage from a first voltage in accordance with the results of a compare operation of the input data and data in a storage device. When the second voltage appears on the matchline and the first voltage appears on a synkline, it is indicated that the data included in all sub-arrays coincides with input data. When the second voltage appears on the synkline, it is indicated that any data of the sub-arrays does not coincide with input data, or an invalid state in a valid memory cell is indicated, and the synkline is kept at the second voltage. When the first sub-array has data being different from input data, the synkline is kept at the second voltage by the above. Further, while the synkline keeps the second voltage, the matchline is kept at the second voltage.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种地址存储器（CAM），其中预充电次数减少，并且能够降低功率消耗，从而确保高速操作。 解决方案：根据存储设备中的输入数据和数据的比较操作的结果，将synkline和匹配线从第一电压复位到第二电压。 当第二个电压出现在匹配线上，第一个电压出现在同步线上时，表明包括在所有子阵列中的数据与输入数据一致。 当synkline上出现第二个电压时，表示子阵列的任何数据与输入数据不一致，或指示有效存储单元中的无效状态，并且synkline保持在第二电压。 当第一子阵列具有与输入数据不同的数据时，通过上述将同步线保持在第二电压。 此外，当同步线保持第二电压时，匹配线保持在第二电压。