公开(公告)号：GB2549906B

公开(公告)日：2021-07-28

申请号：GB201712265

申请日：2015-12-16

Applicant: IBM

Inventor： JEFFREY BROWNSCHEIDLE ,  DUNG QUOC NGUYEN ,  MAUREEN ANNE DELANEY ,  SUNDEEP CHADHA ,  HUNG QUI LE ,  BRIAN WILLIAM THOMPTO

IPC: G06F9/38

Abstract: An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.

公开(公告)号：GB2549906A

公开(公告)日：2017-11-01

申请号：GB201712265

申请日：2015-12-16

Applicant: IBM

Inventor： JEFFREY BROWNSCHEIDLE ,  DUNG QUOC NGUYEN ,  MAUREEN ANNE DELANEY ,  SUNDEEP CHADHA ,  HUNG QUI LE ,  BRIAN WILLIAM THOMPTO

IPC: G06F9/38

Abstract: An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.