公开(公告)号：JPH07320249A

公开(公告)日：1995-12-08

申请号：JP5749995

申请日：1995-03-16

Applicant: IBM

Inventor： RANDOORU TOMASU KAASU ,  JIYON JIYOOZEFU KOTORA

IPC: B28D5/00 ,  B28D5/02 ,  G11B5/127 ,  G11B5/31 ,  G11B5/60 ,  G11B21/00 ,  G11B21/21

Abstract: PURPOSE: To minimize the operation of each element by forming a plurality of first channels in specified depth to a first flat surface on a wafer and slicing each line of a device from the wafer. CONSTITUTION: A plurality of vertical channels 41 are notched to the deposit surface of a wafer 36. It is favorable that the channel 41 has depth less than the half of the wafer 36. The channels are formed, and the wafer is removed from a holder, turned upside down, and mounted again. The channels are cut to the reverse surface, preferably depth less than the half of the wafer 36 of the wafer 36. Each channel is aligned with channels on the reverse side of the wafer 36. Since the total of each depth of an aligned channel pair is made smaller than the thickness of the whole wafer, the connecting sections of a substrate are left among device columns. The lines of sliders are sliced from the horizontal edge 33 of a wafer 31. Each line bar can be mounted on a working plane for succeeding line working.