公开(公告)号：DE1524424A1

公开(公告)日：1970-04-02

申请号：DE1524424

申请日：1966-10-14

Applicant: IBM

Inventor： JOHN BAUMGARTNER RICHARD ,  FREDERICK BOND MILTON

IPC: G06K9/34 ,  G06K9/00

Abstract: 1,144,319. Character recognition. INTERNATIONAL BUSINESS MACHINES CORP. 24 Oct., 1966 [24 Oct., 1965], No. 47521/66. Heading G4R. In a character recognition system, the pitch of successive characters to be scanned is determined and each character space is divided into areas accordingly, signals from scanning the character being tested in each area to determine when the character has been scanned to enable character recognition circuitry. In Fig. 1, a flying-spot scanner 10 &c. scans the character from right to left in a raster of vertical one-column scans. The video signal produced is digitized 30 and fed through two one-scan "look-ahead" shift registers LA-1, LA-2 in turn, to a multi-scan shift register 39 into which it is gated when a "character present" signal is on. Circuit 40 is responsive to registers LA-1, LA-2 to produce the "character present" signal in response to two adjacent "black" bits in each of two adjacent scans. The "character present" signal also enables "segmentation" circuits 300 and an "invalid video" circuit 650. It is turned off in response to any one of a number of signals indicating end of character, produced e.g. by "segmentation" circuits 300, or to an "invalid video" output from circuit 650. Circuits 50, 112, 140, 200 determine the character pitch (character centre to character centre), produce signals effectively dividing the character into overlapping areas horizontally and detect any blank character space. The area identifying signals produced partially control the "segmentation" circuits 300 which recognize the boundary between characters according to one or other of a number of criteria operating on information from the shift registers LA-1, LA-2, 39. When the boundary is recognized by any one of the criteria, the contents of shift register 39 are passed to character recognition circuitry 675 which can be as in Specification 1,102,359, which is referred to. Character pitch determination.-For each pair of successive characters separately, a pitch ring-counter (68, Fig. 3, not shown) measures the pitch between the centres of the two characters by counting half the number of scans to cross the characters and all the scans to cross the gap between them, counter input being partly under control of the "character present" signal and its inverse. A marking on one of four lines from the scanner control 20, specifying the scanner pitch i.e. the horizontal distance between successive scans, gates respective outputs of the counter (68) to flip-flops (96-99) to produce signals to specify the character pitch. Pitch counters 113, 135, 136, 137 count the numbers of character pairs having respective ones of four possible character pitches. A circuit (Fig. 8, not shown) dynamically specifies as the current character pitch that pitch having the largest count, provided this is greater than three. If two equal counts (each greater than three) are the largest, the pitch representing the larger character-centre-to-character-centre distance is chosen. If all the counts are three or less, a predetermined one (10) of the pitches is chosen irrespective of which count is largest. Division of character into areas and detection of blank character space.-An auxiliary binary counter (225, Fig. 9, not shown) counts scans in the presence of the "character present"signal. On reaching a count of 7 for the first time during a character it sets a second binary counter (210) to 7. This second counter can also count scans and is reset by detection of a blank character space or various segmentation signals. When the second counter (210) attains a reading of 7 by whatever means it stops and enables further scans to be counted by a ring counter (205). When the latter reaches its fifth stage, an extra four pulses are gated in if a period or hyphen bit pattern is detected in the shift register 39, thereby accelerating the area condition required to activate the MINAND and PRODIF segmentation circuits (details of the latter below). Logic (241-257, 260, 263 &c.) responds to the scan pitch and character pitch signals and the stages of the ring counter (205) to set latches producing area 1, 2 and 3 signals in that order as respective positions across the character width are reached during scanning. If the "character present" signal is absent when area 3 is reached, a "blank character space" signal is produced. An "end of character area" signal is produced two scans after the area 3 signal, using a binary counter (267). Segmentation circuits.-The "end of character area" signal mentioned just above will cause segmentation of one character from the next and gating of the shift register 39 to the recognition circuitry 675 as a last resort, but normally this is done by one of the segmentation circuits described now. (The first three circuits have elements in common). THREE BLANK SCANS. A segmentation signal is produced in response to at least 7 scans having been made and three adjacent scans each containing either (outside area 2) no black bit or (inside area 2) no two adjacent black bits, the circuit being responsive to the registers LA-1, LA-2, and the first column of shift register 39 for this purpose (Fig. 10, not shown). ONE BLANK SCAN. A segmentation signal is produced in response to being in area 1 and a scan containing either (outside area 2) no black bit or (inside area 2) no two adjacent black bits, the circuit being responsive to register LA-2 for this purpose (Fig. 10, not shown). NOT ANDED. A segmentation signal is produced in response to being in area 2 and two adjacent scans containing no pair of adjacent black bits, one in each scan, the circuit being responsive to register LA-2 and the first column of register 39 for this purpose (Fig. 10, not shown). SERPENTINE WTHITE. A segmentation signal is produced in area 2 in response to a continuous path of white bits passing from the raster top to the raster bottom is not more than three scans. The circuit responds to the first two columns of register 39 and to register LA-2 to produce this signal unless a horizontal or diagonal straight line of three black bits is detected (Fig. 11, not shown). MINAND. The circuit (Fig. 12, not shown) responds to the registers LA-1, LA-2 and the first column of register 39 (LA1-1, LA2-1, SR1-1) to detect pairs of horizontally adjacent black bits ("adjacencies"). Initially, adjacencies having a black bit in each of LA-1 and LA-2 are counted negatively in a first binary counter (346) and adjacencies having a black bit in each of LA-2 and the first column of register 39 are counted positively in the counter (346), except that when both sorts of adjacency occur together (i.e. three black bits,) as they do at the left-hand edge of some upper-case characters, the first counter (346) is not altered but a second binary counter (352) is incremented by unity. A positive count of two or more in the first counter (346) together with a count of less than 12 in the second counter (352) will produce (348) a signal. The first occurrence of this signal will reverse a latch (326) with the result that adjacencies previously counted positively and negatively in the first counter (346) will now be counted negatively and positively respectively and any second occurrence of said signal will produce a segmentation signal (331). The counters (346, 352) are reset each scan. PRODIF. The circuit (Fig. 13) produces a segmentation signal for touching or nearly touching characters. The third positions from the top of the 13 columns of register 39 are ORed at 360. Bits 1 (blacks) from OR 360 are counted at 365 and bits 0 reset counter 365 , until a count of 7 is reached. Counter 365 is also reset each scan. Bits 1 from OR 360 also go to AND 373 which also receives the output of OR 372 which is fed from the bottom positions of the first 12 columns of register 39. Thus, except during the top and bottom 3 rows of character, AND 373 enables ANDs 400, 381, 399, 376 in area 2 to pass inputs from the third positions from the top, LA1-3, SR1-3, ofregiste LA-1 and of the first column of register 39, to be counted at 371, under control of a latch 378. Initially latch 378 is reset so LA1-3 ones and alternate SR1-3 ones are counted negatively and positively respectively, latch 370 performing the halving for SR1-3. A positive final count (for a scan) causes AND 393 to set a latch 394. AND 395A will produce an outflow in response to a plus sign in counter 371 (which could be a count of zero since the counter is reset to +0), together with a latch 395 being set to indicate that at least one LA1-3 one has been applied. Setting of latch 394 or an output from AND 395A produces an output from OR 396 to set latch 378 provided the character height is at least 7 bits as indicated by counter 365. Setting of latch 378 reverses the roles of LA1-3 and SR1-3 in their effect on counter 371 for the next scan. A further output from OR 396 produces a segmentation signal at 401. If the latch 378 is not set by area 3, the area 3 signal sets it. The top and bottom 3 rows of character are not used in the counting at 371 because serifs tend to occur in these regions. A count of less than 3 in counter 365 resets counter 371 and latches 370, 394, 395 to prevent video noise patterns being considered as the bottom of the character. In essence, the PRODIF circuit looks for a scan flanked by two scans each having at least twice as many blanks. CHOPS. This circuit (Fig. 14, not shown) produces a segmentation signal particularly when adjacent characters are touching and at least one of them has a side curving towards the other. In a given scan, a black detected in the third position from the top of register LA-1 sets a control latch (475) to enable a binary counter (477) to count bit clock pulses, and blacks in the third and fourth positions from the top of register LA-1 in conjunction with whites in the first and second are detected by an AND gate (487A) t

公开(公告)号：DE1549764A1

公开(公告)日：1971-04-15

申请号：DE1549764

申请日：1967-05-06

Applicant: IBM

Inventor： RICHARD ANDREWS DOUGLAS ,  JOSEPH ATRUBIN ALLAN ,  JOHN BAUMGARTNER RICHARD ,  FREDERICK BOND MILTON ,  HU KUANG-CHI

IPC: G06K9/34 ,  G06K9/04

Abstract: 1,179,916. Pattern recognition. INTERNATIONAL BUSINESS MACHINES CORP. 24 April, 1967 [9 May, 1966], No. 18704/67. Heading G4R. In pattern recognition apparatus, pattern data is passed progressively through a storage device, the boundary between adjacent patterns is determined, and portions of a pattern overlying an adjacent pattern are removed from a predetermined plurality of storage positions when all the data representative of a pattern is in the storage device and data elements are present in a predetermined plurality of storage positions, the pattern data being passed to recognition means without the removed portions. A flying spot scanner reads a line of characters starting at the right hand end, each character being read in a series of vertical scans (columns), the read data being passed through a 5-scan look-ahead shift register LA1-LA5 and then into a 15-scan main shift register 17 which feeds character recognition circuitry which may be as in Specification 1,102,359 which is referred to. A segmentation circuit 19 which may be as in Specification 1,144,319 which is referred to, responds to the shift registers to produce a segmentation signal indicating that the boundary between two adjacent characters as in register column LA3. AND gates 22, 23 are fed from stages of the look-ahead register and main register to detect conflict of adjacent characters. The conflict may be overhanging, underhanging, abutting or overlap. The bottom 6 bit stages of register columns LA3, LA4 are cleared if AND 22 produces an output (while AND 23 does not) during the first scan after the segmentation, signal, and also if AND 23 produces an output during the third scan after the segmentation signal, via OR 27. Thus conflicting bits are destroyed. Normally data shifted from the look-ahead register passes via AND 33 into the first column of the main register but during the fourth scan after the segmentation signal it is passed instead via AND 31 to auxiliary register 21, a blank "scan" being entered into the first column of the main register. The segmentation signal, 4 scans delayed, causes the recognition circuitry to recognise the character now in the main register which is cleared at the end of the fourth scan following the segmentation signal. During the next scan, the contents of the auxiliary register 21 are passed via AND 35 into the second column of the main register while the output from register column LA5 recommences to pass via AND 33 into the first column of the main register. Fig. 5 (not shown) shows a modification in which conflicting bits destroyed in the lookahead register are first transferred to corresponding bit positions of the first two columns of a 3-scan auxiliary register which replaces that of Fig. 2. During the scan after clearing of the main register referred to, the contents of the 3 auxiliary register columns are passed to columns 2, 3, 4 of the main register and the output from register column LA5 recommences to pass into the first column of the main register.