公开(公告)号：WO2008083906A3

公开(公告)日：2009-02-26

申请号：PCT/EP2007064261

申请日：2007-12-19

Applicant: IBM ,  IBM UK ,  BERRY ROBERT WALTER JR ,  JOHNS CHARLES RAY ,  KURUTS CHRISTOPHER

Inventor： BERRY ROBERT WALTER JR ,  JOHNS CHARLES RAY ,  KURUTS CHRISTOPHER

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/266 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3891 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20

Abstract: A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from thepower systemexceeds a predetermined threshold power. The power systemmay reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actualoutput voltage that processor circuitryreceives from the power system in comparison to an expected output voltage over time and corrects for such variance.

Abstract translation: 电力系统耦合到多核处理器以向处理器供电。 当处理器从电力系统消耗的功率获得预定的阈值功率时，电力系统节流处理器的至少一个核心。 电力系统可以降低特定核心或时钟门指令发出的速度，以提供功率节流。 电力系统动态地响应处理器电路从电力系统接收的实际输出电压的变化，与期望的输出电压相比较，并且校正这种差异。

公开(公告)号：EP1370968A4

公开(公告)日：2010-03-03

申请号：EP02705343

申请日：2002-03-19

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  TOSHIBA KK ,  IBM

Inventor： SUZUOKI MASAKAZU ,  YAMAZAKI TAKESHI ,  HOFSTEE HARM PETER ,  HOPKINS MARTIN E ,  JOHNS CHARLES RAY ,  KAHLE JAMES ALLAN ,  ASANO SHIGEHIRO ,  KUNIMATSU ATSUSHI

IPC: G06F9/48 ,  G06F15/16 ,  G06F9/44 ,  G06F9/50 ,  G06F15/177 ,  G06F15/80 ,  H04L29/06 ,  H04L29/08

CPC classification number: G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

公开(公告)号：WO2007020274A3

公开(公告)日：2007-04-19

申请号：PCT/EP2006065372

申请日：2006-08-16

Applicant: IBM ,  IBM UK ,  DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIBERTY JOHN SAMUEL ,  SWANSON TODD ,  TRUONG THUONG QUANG

Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIBERTY JOHN SAMUEL ,  SWANSON TODD ,  TRUONG THUONG QUANG

IPC: G06F13/28 ,  G06F15/163 ,  H04Q3/545

CPC classification number: G06F13/28

Abstract: A system and method for communicating instructions and data between a processor and external devices are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power "stall" state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract translation: 提供了一种用于在处理器和外部设备之间传送指令和数据的系统和方法。 系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或者没有可用空间来写入对应的寄存器时，处理器处于低功率“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。

公开(公告)号：WO2007104638A3

公开(公告)日：2007-12-13

申请号：PCT/EP2007051810

申请日：2007-02-26

Applicant: IBM ,  IBM UK ,  JOHNS CHARLES RAY

Inventor： JOHNS CHARLES RAY

IPC: G06F9/46

CPC classification number: G06F12/0842 ,  G06F9/30043 ,  G06F9/3834 ,  G06F2212/1016 ,  G06F2212/1032

Abstract: A method, system, apparatus, and article of manufacture for performing cacheline polling utilizing a store and reserve instruction are disclosed. In accordance with one embodiment of the present invention, a first process initially requests an action to be performed by a second process. A reservation is set at a cacheable memory location via a store operation. The first process reads the cacheable memory location via a load operation to determine whether or not the requested action has been completed by the second process. The load operation of the first process is stalled until the reservation on the cacheable memory location is lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.

Abstract translation: 公开了一种使用存储和预约指令执行高速缓存行轮询的方法，系统，装置和制品。 根据本发明的一个实施例，第一过程最初请求通过第二过程执行动作。 通过存储操作在可高速缓存的存储器位置设置预留。 第一进程通过加载操作读取可缓存的存储器位置，以确定所请求的动作是否已由第二进程完成。 第一进程的加载操作停止，直到可缓存的存储器位置的预留丢失。 在所请求的动作已经完成之后，可缓存存储器位置中的预留由第二进程复位。

公开(公告)号：WO2006095838A3

公开(公告)日：2007-02-15

申请号：PCT/JP2006304659

申请日：2006-03-02

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： CLARK SCOTT DOUGLAS ,  JOHNS CHARLES RAY ,  KROLAK DAVID JOHN ,  YAMAZAKI TAKESHI ,  BROWN JEFFREY DOUGLAS

IPC: G06F13/362

CPC classification number: G06F13/362 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151

Abstract: A data switch, a method and a computer program are provided for the transfer of data between multiple bus units in a memory system. Each bus unit is connected to a corresponding data ramp. Each data ramp is only directly connected to the adjacent data ramps. This forms at least one data ring that enables the transfer of data from each bus unit to any other bus unit in the memory system. A central arbiter manages the transfer of data between the data ramps and the transfer of data between the data ramp and its corresponding bus unit. A preferred embodiment contains four data rings, wherein two data rings transfer data clockwise and two data rings transfer data counter-clockwise.

Abstract translation: 数据交换机，方法和计算机程序被提供用于在存储器系统中的多个总线单元之间传输数据。 每个总线单元连接到相应的数据斜坡。 每个数据斜坡只直接连接到相邻的数据斜坡。 这形成至少一个数据环，该数据环能够将数据从每个总线单元传送到存储器系统中的任何其他总线单元。 中央仲裁器管理数据斜坡和数据斜坡及其相应总线单元之间的数据传输之间的数据传输。 一个优选实施例包含四个数据环，其中两个数据环顺时针传输数据，两个数据环逆时针传输数据。

公开(公告)号：JP2007249960A

公开(公告)日：2007-09-27

申请号：JP2007039392

申请日：2007-02-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JOHNS CHARLES RAY

IPC: G06F12/08 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/526

Abstract: PROBLEM TO BE SOLVED: To provide a method, device and program for performing cacheline polling using store with reserve and load when reservation lost, instructions.
SOLUTION: In one embodiment, a method is provided including steps of storing a buffer flag busy indicator data value within a first cacheable memory location and setting a load/store operation reservation on the first cacheable memory location via the store and reserve instructions. A data value stored within the first cacheable memory location is accessed via conditional read instructions in response to a determination that the load/store operation reservation on the first cacheable memory location has been reset. Conversely, execution of the conditional load instructions is stopped in response to a determination that the load/store operation reservation on the first cacheable memory location has not been reset.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种方法，设备和程序，用于在预留丢失时使用具有预留和负载的存储进行高速缓存线轮询，指令。 解决方案：在一个实施例中，提供了一种方法，包括以下步骤：将缓冲器标志繁忙指示符数据值存储在第一可缓存存储器位置内，并经由存储和预约指令在第一可缓存存储器位置上设置加载/存储操作预留 。 响应于第一可缓存存储器位置上的加载/存储操作预留被重置的确定，通过条件读取指令来存储存储在第一可缓存存储器位置内的数据值。 相反，响应于第一可缓存存储器位置上的加载/存储操作预留未被重置的确定停止执行条件加载指令。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2007085522A3

公开(公告)日：2008-06-26

申请号：PCT/EP2007050182

申请日：2007-01-09

Applicant: IBM ,  IBM UK ,  BROKENSHIRE DANIEL ALAN ,  JOHNS CHARLES RAY ,  MINOR BARRY ,  NUTTER MARK RICHARD

Inventor： BROKENSHIRE DANIEL ALAN ,  JOHNS CHARLES RAY ,  MINOR BARRY ,  NUTTER MARK RICHARD

IPC: G06F15/167

CPC classification number: G06F15/17337

Abstract: An apparatus and method for efficient communication of producer/consumer buffer status are provided. With the apparatus and method, devices in a data processing system notify each other of updates to head and tail pointers of a shared buffer region when the devices perform operations on the shared buffer region using signal notification channels of the devices. Thus, when a producer device that produces data to the shared buffer region writes data to the shared buffer region, an update to the head pointer is written to a signal notification channel of a consumer device. When a consumer device reads data from the shared buffer region, the consumer device writes a tail pointer update to a signal notification channel of the producer device. In addition, channels may operate in a blocking mode so that the corresponding device is kept in a low power state until an update is received over the channel.

Abstract translation: 提供了用于生产者/消费者缓冲器状态的有效通信的装置和方法。 利用该设备和方法，当设备使用设备的信号通知通道在共享缓冲区域上执行操作时，数据处理系统中的设备通知彼此对共享缓冲区域的头和尾指针的更新。 因此，当向共享缓冲区域产生数据的生成器设备将数据写入到共享缓冲区域时，对头指针的更新被写入消费者设备的信号通知通道。 当消费者设备从共享缓冲区域读取数据时，消费者设备将尾指针更新写入生成器设备的信号通知通道。 此外，信道可以以阻塞模式操作，使得对应的设备保持在低功率状态，直到通过信道接收到更新。

公开(公告)号：WO2007020264B1

公开(公告)日：2007-10-11

申请号：PCT/EP2006065326

申请日：2006-08-15

Applicant: IBM ,  IBM UK ,  BURNS ADAM PATRICK ,  DAY MICHAEL NORMAN ,  FLACHS BRIAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  LIBERTY JOHN SAMUEL

Inventor： BURNS ADAM PATRICK ,  DAY MICHAEL NORMAN ,  FLACHS BRIAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  LIBERTY JOHN SAMUEL

IPC: G06F12/06

CPC classification number: G06F12/0661 ,  G06F12/0223

Abstract: A system and method for limiting the size of a local storage of a processor are provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract translation: 提供了用于限制处理器的本地存储器的大小的系统和方法。 提供与处理器相关联的设施以设置本地存储大小限制。 该设施是一个特权设施，只能通过在多处理器系统中的控制处理器上运行的操作系统或相关处理器本身访问。 当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。 当处理器使用请求地址访问本地存储器时，将与请求地址对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模是 用于访问本地存储。

公开(公告)号：WO2007062984B1

公开(公告)日：2007-09-27

申请号：PCT/EP2006068519

申请日：2006-11-15

Applicant: IBM ,  IBM UK ,  AGUILAR MAXIMINO JR ,  JOHNS CHARLES RAY ,  NUTTER MARK RICHARD ,  STAFFORD JAMES MICHAEL

Inventor： AGUILAR MAXIMINO JR ,  JOHNS CHARLES RAY ,  NUTTER MARK RICHARD ,  STAFFORD JAMES MICHAEL

IPC: G06F1/20

CPC classification number: G06F1/206 ,  G01K3/005 ,  G01K7/015

Abstract: A computer implemented method, data processing system, computer usable code, and apparatus are provided for generation of software thermal profiles for applications executing on a set of processors. Sampling is performed of the hardware operations occurring in a set of processors during the execution of a set of workloads to create sampled information. A thermal index is then generated based on the sampled information.

Abstract translation: 提供了计算机实现的方法，数据处理系统，计算机可用代码和装置，用于为在一组处理器上执行的应用程序产生软件热分布图。 在执行一组工作负载以创建采样信息期间，执行对一组处理器中发生的硬件操作的采样。 然后基于采样信息生成热指数。

公开(公告)号：WO2007062984A3

公开(公告)日：2007-07-12

申请号：PCT/EP2006068519

申请日：2006-11-15

Applicant: IBM ,  IBM UK ,  AGUILAR MAXIMINO JR ,  JOHNS CHARLES RAY ,  NUTTER MARK RICHARD ,  STAFFORD JAMES MICHAEL

Inventor： AGUILAR MAXIMINO JR ,  JOHNS CHARLES RAY ,  NUTTER MARK RICHARD ,  STAFFORD JAMES MICHAEL

IPC: G06F1/20

CPC classification number: G06F1/206 ,  G01K3/005 ,  G01K7/015

Abstract: A computer implemented method, data processing system, computer usable code, and apparatus are provided for generation of software thermal profiles for applications executing on a set of processors. Sampling is performed of the hardware operations occurring in a set of processors during the execution of a set of workloads to create sampled information. A thermal index is then generated based on the sampled information.