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    SINGLE PORT/MULTIPLE RING IMPLEMENTATION OF A DATA SWITCH
    1.
    发明申请
    SINGLE PORT/MULTIPLE RING IMPLEMENTATION OF A DATA SWITCH 审中-公开
    单端口/数据交换机的多环执行

    公开(公告)号：WO2006095838B1

    公开(公告)日：2007-03-15

    申请号：PCT/JP2006304659

    申请日：2006-03-02

    Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

    Inventor： CLARK SCOTT DOUGLAS ,  JOHNS CHARLES RAY ,  KROLAK DAVID JOHN ,  YAMAZAKI TAKESHI ,  BROWN JEFFREY DOUGLAS

    IPC: G06F13/362

    CPC classification number: G06F13/362 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151

    Abstract: A data switch, a method and a computer program are provided for the transfer of data between multiple bus units in a memory system. Each bus unit is connected to a corresponding data ramp. Each data ramp is only directly connected to the adjacent data ramps. This forms at least one data ring that enables the transfer of data from each bus unit to any other bus unit in the memory system. A central arbiter manages the transfer of data between the data ramps and the transfer of data between the data ramp and its corresponding bus unit. A preferred embodiment contains four data rings, wherein two data rings transfer data clockwise and two data rings transfer data counter-clockwise.

    Abstract translation: 提供数据开关，方法和计算机程序用于在存储器系统中的多个总线单元之间传送数据。 每个总线单元连接到相应的数据斜坡。 每个数据斜坡仅直接连接到相邻的数据斜坡。 这形成至少一个数据环，其使得能够将数据从每个总线单元传送到存储器系统中的任何其它总线单元。 中央仲裁器管理数据斜坡之间的数据传输和数据斜坡与其相应总线单元之间的数据传输。 优选实施例包含四个数据环，其中两个数据环顺时针传送数据，两个数据环逆时针传送数据。

    SINGLE PORT/MULTIPLE RING IMPLEMENTATION OF A DATA SWITCH
    2.
    发明申请
    SINGLE PORT/MULTIPLE RING IMPLEMENTATION OF A DATA SWITCH 审中-公开
    数据交换的单端口/多环实现

    公开(公告)号：WO2006095838A3

    公开(公告)日：2007-02-15

    申请号：PCT/JP2006304659

    申请日：2006-03-02

    Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

    Inventor： CLARK SCOTT DOUGLAS ,  JOHNS CHARLES RAY ,  KROLAK DAVID JOHN ,  YAMAZAKI TAKESHI ,  BROWN JEFFREY DOUGLAS

    IPC: G06F13/362

    CPC classification number: G06F13/362 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151

    Abstract: A data switch, a method and a computer program are provided for the transfer of data between multiple bus units in a memory system. Each bus unit is connected to a corresponding data ramp. Each data ramp is only directly connected to the adjacent data ramps. This forms at least one data ring that enables the transfer of data from each bus unit to any other bus unit in the memory system. A central arbiter manages the transfer of data between the data ramps and the transfer of data between the data ramp and its corresponding bus unit. A preferred embodiment contains four data rings, wherein two data rings transfer data clockwise and two data rings transfer data counter-clockwise.

    Abstract translation: 数据交换机，方法和计算机程序被提供用于在存储器系统中的多个总线单元之间传输数据。 每个总线单元连接到相应的数据斜坡。 每个数据斜坡只直接连接到相邻的数据斜坡。 这形成至少一个数据环，该数据环能够将数据从每个总线单元传送到存储器系统中的任何其他总线单元。 中央仲裁器管理数据斜坡和数据斜坡及其相应总线单元之间的数据传输之间的数据传输。 一个优选实施例包含四个数据环，其中两个数据环顺时针传输数据，两个数据环逆时针传输数据。

    Method and system for low cost maintenance of cache coherence for accelerator
    4.
    发明专利
    Method and system for low cost maintenance of cache coherence for accelerator 有权
    用于加速器的高速缓存的低成本维护方法和系统

    公开(公告)号：JP2007257637A

    公开(公告)日：2007-10-04

    申请号：JP2007071882

    申请日：2007-03-20

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： WOTTRENG ANDREW HENRY ,  CLARK SCOTT DOUGLAS

    IPC: G06F12/08

    CPC classification number: G06F12/0817 ,  G06F2212/1016

    Abstract: PROBLEM TO BE SOLVED: To reduce the consumption of internode bandwidth by communications maintaining coherence between accelerators and CPUs. SOLUTION: The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：通过维护加速器和CPU之间的一致性来减少节间带宽的消耗。 解决方案：CPU和加速器可能会聚集在多处理环境中的单独节点上。 包含共享存储器设备的每个节点可以维护目录以跟踪可能在其他节点处被缓存的共享存储器的块。 因此，只有当存储器位置已被缓存在节点外部时，命令和地址才可以发送到其他节点上的处理器和加速器。 另外，因为加速器通常不能访问与CPU相同的数据，所以只能将初始读，写和同步操作传输到其他节点。 对数据的中间访问可以非相干地执行。 结果，可以减少用于维持一致性所消耗的芯片间带宽。 版权所有（C）2008，JPO＆INPIT

    System to maintain low-cost cache coherency for accelerators
    5.
    发明专利
    System to maintain low-cost cache coherency for accelerators 有权
    为加速器维护低成本缓存的系统

    公开(公告)号：JP2012181860A

    公开(公告)日：2012-09-20

    申请号：JP2012106285

    申请日：2012-05-07

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： WOTTRENG ANDREW HENRY ,  CLARK SCOTT DOUGLAS

    IPC: G06F12/08

    CPC classification number: G06F12/0817 ,  G06F2212/1016

    Abstract: PROBLEM TO BE SOLVED: To reduce consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs.SOLUTION: CPUs 210 and accelerators 220 may be clustered on separate nodes in a multiprocessing environment. Each node 0, 1 that contains a shared memory device 212, 222 may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, command and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, inter-chip bandwidth consumed for maintaining coherence may be reduced.

    Abstract translation: 要解决的问题：通过维护加速器和CPU之间的一致性来减少节点间带宽的消耗。 解决方案：CPU 210和加速器220可以聚集在多处理环境中的单独的节点上。 包含共享存储器设备212,222的每个节点0,1可以维护目录以跟踪可能已经在其他节点处被缓存的共享存储器的块。 因此，只有当存储器位置已被缓存在节点之外时，命令和地址才可以发送到其他节点处的处理器和加速器。 另外，因为加速器通常不能访问与CPU相同的数据，所以只能将初始读，写和同步操作传输到其他节点。 对数据的中间访问可以非相干地执行。 结果，可以减少用于维持一致性所消耗的芯片间带宽。 版权所有（C）2012，JPO＆INPIT

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