公开(公告)号：DE2657643A1

公开(公告)日：1977-07-14

申请号：DE2657643

申请日：1976-12-20

Applicant: IBM

Inventor： CHRISTIE KENNETH HOWARD ,  DEWITT DAVID ,  JOHNSON WILLIAM STANFORD

IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/336 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

Abstract: A metal nitride oxide semiconductor device capable of use within a memory cell, having a more heavily doped region of the same type as the substrate provided directly under the channel of the depletion mode device. Application of a positive write voltage to the gate of the device, with the substrate at 0 volts potential and the source and drain biased to a suitable positive level, results in avalanche operation of the device whereby charge is stored in a nitride oxide interface under the gate, thereby converting the device to enhancement mode operation. The charge can be removed with the source and drain biased to the 0 volt potential of the substrate and a positive erase signal applied to the gate. A four device memory cell is disclosed.

公开(公告)号：DE2425382A1

公开(公告)日：1975-01-02

申请号：DE2425382

申请日：1974-05-25

Applicant: IBM

Inventor： JOHNSON WILLIAM STANFORD ,  KU SAN-MEI

IPC: H01L21/283 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/322 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/00 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

Abstract: A method for manufacturing insulated gate field effect transistor devices utilizing ion implantation for elimination and suppression of mobile ion contamination is described and comprises bombarding and implanting hydrogen or helium into the dielectric insulating layer of an insulated gate field effect transistor at relatively low ion energy, followed by a comparatively low temperature anneal.

公开(公告)号：DE2626739A1

公开(公告)日：1977-01-20

申请号：DE2626739

申请日：1976-06-15

Applicant: IBM

Inventor： JOHNSON WILLIAM STANFORD

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/762 ,  H01L27/12 ,  H01L21/76

Abstract: An integrated circuit structure with full dielectric isolation, i.e., the electrical isolation is provided by electrically insulative material, is formed by ion bombarding a silicon substrate with ions such as nitrogen, oxygen or carbon to implant subsurface region containing such ions and heating the resulted bombarded substrate to a temperature sufficient to react the introduced ions with the substrate to form a subsurface layer which has a different etchability than silicon. An epitaxial layer of monocrystalline silicon is then deposited on the substrate, after which a pattern of regions of electrically insulating material is formed extending through the epitaxial layer beyond the substrate surface into contact with the subsurface layer to laterally surround a plurality of pockets in said silicon. An electrically insulative layer is formed on the surface of the epitaxial layer continuous with the electrically insulating lateral regions. The silicon substrate below the subsurface layer is removed by etching in a solvent in which silicon is more etchable than is the subsurface layer to expose the subsurface layer, and the subsurface layer is etched away with a solvent in which this layer is more etchable than are the lateral regions of electrically insulating material. As a result, the planar surfaces of the silicon pockets are exposed, and selective conductivity-determining impurities may be introduced into the silicon pockets to form the devices of the integrated circuit.

公开(公告)号：DE2430023A1

公开(公告)日：1975-01-30

申请号：DE2430023

申请日：1974-06-22

Applicant: IBM

Inventor： JOHNSON WILLIAM STANFORD

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L27/088 ,  H01L27/10

Abstract: The invention is concerned with methods for producing improved semiconductor devices. The invention is advantageously employable in the fabrication of insulated-gate field-effect transistor devices. The problem of accurately aligning the gate electrode over the channel region, lying between the source region and the drain region of a field effect transistor, is particularly addressed and solved. Accurate and precise field protection of all areas of the field-effect transistor surrounding the channel, source and drain regions is simply and effectively accomplished. The proper alignment of the gate electrode is largely accomplished by utilizing essentially the same mask structure to define the gate, source and drain regions. The same mask structure is utilized to define the area that is field protected.