1.
    发明专利
    未知

    公开(公告)号:DE60311528D1

    公开(公告)日:2007-03-15

    申请号:DE60311528

    申请日:2003-10-28

    Applicant: IBM

    Abstract: An apparatus for data transmission over a network includes a buffer and a timer mechanism for timing an optimum interval (less than the round-trip error response delay) for retransmission of data. A first accessor accesses data in the buffer for transmission and starts a first timeout clock. Second or further accessors of the buffer are responsive to a timeout to access the data, start a timeout clock and attempt to transmit the data on a path avoiding path elements used by prior accessors. A counter increments and decrements a count of the references to the buffer by accessors and signals when the count reaches zero. A memory manager returns the buffer to a free buffer pool responsive to the reference counter signaling that the count has reached zero. An analysis mechanism can be used to determine the optimum interval and tune the timer mechanism.

    2.
    发明专利
    未知

    公开(公告)号:DE60311528T2

    公开(公告)日:2007-10-31

    申请号:DE60311528

    申请日:2003-10-28

    Applicant: IBM

    Abstract: An apparatus for data transmission over a network includes a buffer and a timer mechanism for timing an optimum interval (less than the round-trip error response delay) for retransmission of data. A first accessor accesses data in the buffer for transmission and starts a first timeout clock. Second or further accessors of the buffer are responsive to a timeout to access the data, start a timeout clock and attempt to transmit the data on a path avoiding path elements used by prior accessors. A counter increments and decrements a count of the references to the buffer by accessors and signals when the count reaches zero. A memory manager returns the buffer to a free buffer pool responsive to the reference counter signaling that the count has reached zero. An analysis mechanism can be used to determine the optimum interval and tune the timer mechanism.

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