公开(公告)号：AU2003278357A1

公开(公告)日：2004-08-23

申请号：AU2003278357

申请日：2003-10-28

Applicant: IBM

Inventor： SCALES WILLIAM JAMES ,  FUENTE CARLOS FRANCISCO ,  JONES ROBERT MICHAEL ,  PASSINGHAM WILLIAM JOHN

IPC: H04L45/24 ,  H04L45/28 ,  H04L12/56

Abstract: An apparatus for data transmission over a network includes a buffer and a timer mechanism for timing an optimum interval (less than the round-trip error response delay) for retransmission of data. A first accessor accesses data in the buffer for transmission and starts a first timeout clock. Second or further accessors of the buffer are responsive to a timeout to access the data, start a timeout clock and attempt to transmit the data on a path avoiding path elements used by prior accessors. A counter increments and decrements a count of the references to the buffer by accessors and signals when the count reaches zero. A memory manager returns the buffer to a free buffer pool responsive to the reference counter signaling that the count has reached zero. An analysis mechanism can be used to determine the optimum interval and tune the timer mechanism.

公开(公告)号：AT352935T

公开(公告)日：2007-02-15

申请号：AT03769668

申请日：2003-10-28

Applicant: IBM

Inventor： FUENTE CARLOS FRANCISCO ,  JONES ROBERT MICHAEL ,  PASSINGHAM WILLIAM JOHN ,  SCALES WILLIAM JAMES

IPC: H04L45/24 ,  H04L45/28 ,  H04L12/56

Abstract: An apparatus for data transmission over a network includes a buffer and a timer mechanism for timing an optimum interval (less than the round-trip error response delay) for retransmission of data. A first accessor accesses data in the buffer for transmission and starts a first timeout clock. Second or further accessors of the buffer are responsive to a timeout to access the data, start a timeout clock and attempt to transmit the data on a path avoiding path elements used by prior accessors. A counter increments and decrements a count of the references to the buffer by accessors and signals when the count reaches zero. A memory manager returns the buffer to a free buffer pool responsive to the reference counter signaling that the count has reached zero. An analysis mechanism can be used to determine the optimum interval and tune the timer mechanism.

公开(公告)号：GB2342731A

公开(公告)日：2000-04-19

申请号：GB9822219

申请日：1998-10-12

Applicant: IBM

Inventor： FOWLER ROBERT VICTOR ,  JONES ROBERT MICHAEL ,  KEY ANDREW

IPC: G06F11/20 ,  G06F13/00

Abstract: In a data processing system having connected devices, device drivers and device adapters, a device adapter is elected to be the controlling adapter. Requests to a device or devices are transparently routed via the controlling adapter. If a controlling adapter fails, the or one of the remaining device adapters is elected to be the replacement controlling adapter. Requests can continue to be serviced via the replacement controlling adapter, and requests that were in progress at the time of the failure can be reissued for service via the replacement controlling adapter.