公开(公告)号：BR9801432A

公开(公告)日：1999-06-01

申请号：BR9801432

申请日：1998-04-23

Applicant: IBM

Inventor： CHEONG HOICHI ,  JORDAN PAUL JOSEPH ,  LE HUNG QUI

IPC: G06F9/38

Abstract: During operation of a pipelined data processing system, an interruptible instruction table is used to store target identifiers associated with instructions which may result in speculative execution. During operation of the interruptible instruction table, a pointer, referred to as a completing instruction buffer entry pointer, points to a bottom of the interruptible instruction table if that table includes any instruction. An entry at the bottom of the interruptible instruction table is a next instruction to complete. This entry includes a target identifier, referred to as a non-speculative-non-interruptible TID, may be used to release resources held for all prior executed instructions. The data processing system determines the value of the non-speculative-non-interruptible TID to ensure that order determination is preserved and provides a true speculative execution point.

公开(公告)号：MY117126A

公开(公告)日：2004-05-31

申请号：MYPI9801505

申请日：1998-04-03

Applicant: IBM

Inventor： CHEONG HOICHI ,  JORDAN PAUL JOSEPH ,  LE HUNG QUI

IPC: G06F9/06 ,  G06F9/22 ,  G06F9/38

Abstract: A DATA PROCESSING SYSTEM (100) INDICATES THAT AN INSTRUCTION DOES NOT HAVE AVAILABLE DATA BECAUSE OF A CACHE MISS OR BECAUSE OF A NON-CACHE-MISS DELAY. WHEN THE INSTRUCTION IS NOT ABLE TO ACCESS THE AVAILABLE DATA AND A CACHE MISS RESULTS, INSTRUCTIONS WHICH ARE DEPENDENT ON THE ISSUED INSTRUCTION ARE NOT ISSUED. HOWEVER, IF THE LOAD EXECUTION IS DELAYED BECAUSE OF A NON-CACHE-MISS DELAY, THEN THE INSTRUCTIONS WHICH ARE DEPENDENT ON THE ISSUED INSTRUCTION ARE ALSO ISSUED IN ANTICIPATION OF A SUCCESSFUL LOAD INSTRUCTION EXECUTION IN A NEXTTIMING CYCLE. THROUGH THE USE OF THIS ISSUING MECHANISM, THE EFFICIENCY OF THE DATA PROCESSING SYSTEM IS INCREASED AS AN EXECUTION UNIT IS BETTER ABLE TO UTILIZE ITS PIPELINE. (FIG. 2)

公开(公告)号：MX9802611A

公开(公告)日：1998-11-29

申请号：MX9802611

申请日：1998-04-03

Applicant: IBM

Inventor： CHEONG HOICHI ,  JORDAN PAUL JOSEPH ,  LE HUNG QUI

IPC: G06F9/38 ,  G11B03/00

Abstract: Durante la operacion de un sistema procesador de datos canalizado, una tabla de instrucciones interrumpibles se usa para almacenar identificadores de objetivos asociados con instrucciones las cuales pueden resultar en una ejecucion especulativa. Durante la operacion de la tabla de instrucciones interrumpible, un indicador, mencionado como un indicador de entrada de memoria temporal de terminacion de instrucciones, señala a un fondo de la tabla de instrucciones interrumpible si esa tabla incluye alguna instruccion. Una entrada en el fondo de la tabla de instrucciones interrumpible es una siguiente instruccion por completar. Esta entrada incluye un identificador de objetivo, nombrado como la TID no especulativa y no interrumpible, se puede usar para liberar fuentes mantenidas para todas las instrucciones ejecutadas anteriormente. El sistema procesador de datos determina el valor de la TID no especulativa y no interrumpible, para asegurar que se conserve una determinacion de orden y suministre un punto de ejecucion especulativa verdadera.