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公开(公告)号：DE1961338A1
公开(公告)日：1970-06-18
申请号：DE1961338
申请日：1969-12-06
Applicant: IBM
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公开(公告)号：DE1815194A1
公开(公告)日：1969-07-31
申请号：DE1815194
申请日：1968-12-17
Applicant: IBM
Inventor： JOSEPH CHESAREK DONALD , DWAYNE REYNOLDS ZACK
Abstract: 1,214,791. Transistor sawtooth circuits; cathode-ray tube circuits. INTERNATIONAL BUSINESS MACHINES CORP. 7 Jan., 1969 [15 Jan., 1968], No. 860/69. Headings H3T and H4T. A C.R.T. deflection coil (81, 91, Fig. 1, not shown), is supplied with a ramp voltage a, Fig. 5, to which is added at its start a step voltage b which assists deflection of the beam and which terminates when the ramp terminates. The ramp a produces an X-deflection of magnitude AXa and a similar but inverted ramp d produces a Y deflection of magnitude AYa, and to each of these is added a rectangular pulse whose amplitude is respectively proportional to #Xa and #Ya and whose duration is equal to that of the ramp. The resulting signals c and f are applied to the coils and speed up the changes in beam deflection velocity at the start and end of a trace to prevent bright spots. The X and Y deflection signals are supplied in digital form #Xd and #Yd to an input stage (10) which derives the square root of the sum of their squares, and in unit (20) converts this to analogue form; a unit (30) produces therefrom a pulse 31 of duration proportional to the length (and time) of the desired trace (AB, Fig. 2, not shown). This pulse enables integrators (40, 50) to generate the ramps a, d; and also opens gates (41, 51) which pass #Xa and #Ya signals from d/a converters (42, 52) to operational amplifiers (60, 70) which add them to a and b respectively to produce the deflection waveforms e, f. The integrators each include a F.E.T. (45, Fig. 3, not shown) to whose source the #Xa or #Ya signal is applied and to whose gate the gating pulse 31 in applied; the drain is connected through a resistor (44) to an amplifier (46) having Miller feedback (47).
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公开(公告)号：DE1499223A1
公开(公告)日：1970-03-12
申请号：DE1499223
申请日：1965-09-27
Applicant: IBM
Inventor： JOSEPH CHESAREK DONALD , EMANUEL PETERSEN HAROLD
Abstract: 1,119,673. Digital word generator. INTERNATIONAL BUSINESS MACHINES CORP. 24 Sept., 1965 [28 Sept., 1964], No. 40711/65. Heading G4A. A word generator comprises a word-modifying logical matrix interconnecting two registers, to produce in the second register a modified version (determined by selectable preconditioning of the matrix) of the word in the first register, the word in the second register being enterable into the first register for cyclic operation to generate a sequence of words in the second register. A computer or the transmitter and receiver of a communication system may each comprise an m-sequence generator as follows to select bit positions to be associated with individual check bits. An operator presets an A-register and two further registers according to the required first word of the sequence, the number of words in the sequence and the number of times the sequence is to be repeated, respectively. During operation, the A-register controls the setting of a B-register via a matrix of gates controlled by switches preset by the operator in accordance with the Boolean equations to govern the generation. The B-register in turn controls the A-register and its output is sampled to provide the m-sequence. Clock-pulse-driven counters are compared with said further registers to control length and number of sequences.
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