公开(公告)号：FR2396386A1

公开(公告)日：1979-01-26

申请号：FR7818480

申请日：1978-06-13

Applicant: IBM

Inventor： JOSHI L ,  PRICER WILBUR D

IPC: G11C11/403 ,  G11C11/405 ,  G11C11/42 ,  G11C11/419 ,  G11C11/24 ,  G11C11/40

Abstract: A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.