公开(公告)号：RU2183850C2

公开(公告)日：2002-06-20

申请号：RU99123716

申请日：1998-04-03

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON DZHON STIVEN ,  KEJZER DZHON MAJKL ,  LUIS DZHERRI DON

IPC: G06F12/08 ,  G06F12/0831

Abstract: computer engineering. SUBSTANCE: invention specifically refers to performance of reading operations from storage of symmetric multiprocessor computer systems. It is suggested in accordance with method that after loading of information at least two caches of system storage should be marked as those containing joint, invariable copies of information. When interrogating processor sends message showing that it wants to read information one certain cache generates reply which indicates that it is information source. This reply is transferred to cache extracting message from circuit of internal connections that is linked to interrogating processor. Reply is detected by system logic and is directed from it into interrogating processor. Then cache generates information into circuit of internal connections which is connected to interrogating processor. System storage detects message and as rule acts as information source. But reply in this case informs storage of system on fact that cache is information source instead of storage. Since delay in cache storage can be shorter than in system storage then employment of such new protocol enables reading efficiency to be substantially improved. EFFECT: development of improved method of reading operations in multiprocessor computer system. 34 cl, 3 dwg