公开(公告)号：US3233114A

公开(公告)日：1966-02-01

申请号：US9729561

申请日：1961-03-21

Applicant: IBM

Inventor： DEREK ELDRIDGE ,  KENNETH AYLING JOHN ,  ANTONY PROUDMAN

IPC: H03K19/084 ,  H03K19/16

CPC classification number: H03K19/16 ,  H03K19/084

公开(公告)号：DE2057256A1

公开(公告)日：1971-05-27

申请号：DE2057256

申请日：1970-11-21

Applicant: IBM

Inventor： KENNETH AYLING JOHN ,  LEE HUA-TUNG

IPC: G06F11/10 ,  G06F12/16 ,  H03M13/00 ,  H03M13/19 ,  H03K13/24

Abstract: 1316348 Error handling INTERNATIONAL BUSINESS MACHINES CORP 20 Oct 1970 [25 Nov 1969] 49656/70 Heading G4A Data processing apparatus for processing data words containing k data bits and (n - k) check bits according to an (n, k) cyclic code includes (n - k) logic circuits arranged to feed result signals into respective stages of an (n - k) stage register and gating means arranged to feed the register contents and c > n - k data (or data and check) bits at a time into the logic circuits (with zero packing where necessary) according to a pattern defined by (c + n - k) rows out of the first (c+n+# - k) rows (the omitted rows being intermediate rows) of the autonomous matrix for the code so that, for the selected submatrix, gating occurs for each element a ij = 1 from the ith bit to the jth logic circuit where i # c and from the (i - c)th register stage to the jth logic circuit where c

公开(公告)号：DE1956869A1

公开(公告)日：1970-07-23

申请号：DE1956869

申请日：1969-11-12

Applicant: IBM

Inventor： KENNETH AYLING JOHN

IPC: B44D3/18 ,  G11C11/14 ,  G11C11/00