公开(公告)号：DE10213352A1

公开(公告)日：2003-01-16

申请号：DE10213352

申请日：2002-03-26

Applicant: IBM

Inventor： HALLER WILHELM E ,  KESSLER FRIEDHELM ,  NISSLER DIETER ,  WOERNER ALEXANDER

IPC: G06F7/02 ,  G06F9/30 ,  G06F9/34 ,  G06F9/312 ,  G06F9/315

Abstract: Method for testing of two multiple bit numbers for determining whether one of two conditions is fulfilled, either A + 1 equals B or A equals B, whereby the method avoids a remainder carry over by use of a comparison of a remainder value for each of the i bit positions of a number. The invention also relates to a corresponding hardware logic circuit.

公开(公告)号：DE10213352B4

公开(公告)日：2004-11-11

申请号：DE10213352

申请日：2002-03-26

Applicant: IBM

Inventor： HALLER WILHELM E ,  KESSLER FRIEDHELM ,  NISSLER DIETER ,  WOERNER ALEXANDER

IPC: G06F7/02 ,  G06F9/30 ,  G06F9/34 ,  G06F9/312 ,  G06F9/315