中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.017 seconds)

    Method and apparatus for reducing bias temperature instability (bti) effect
    1.
    发明专利
    Method and apparatus for reducing bias temperature instability (bti) effect 有权
    降低偏温不稳定性（BTI）效应的方法和装置

    公开(公告)号：JP2006252696A

    公开(公告)日：2006-09-21

    申请号：JP2005069170

    申请日：2005-03-11

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： AIPPERSPACH ANTHONY GUS ,  HOVIS WILLIAM PAUL ,  KUEPER TERRANCE WAYNE ,  SHEETS JOHN EDWARD II

    IPC: G11C11/413

    Abstract: PROBLEM TO BE SOLVED: To provide a method and an apparatus enabling an electronic system implemented using a field effect transistor (FET) to reduce a threshold voltage shift due to bias temperature instability (BTI).
    SOLUTION: The VT shift due to BTI is accumulated when a FET is in a particular voltage stress state. A number of memory elements in the electronic system store the same data over substantially the life of the system. As a result, the VT shift due to BTI significantly occurs in a FET in the memory element. An embodiment of the present invention guarantees that a specific memory element is in a first state for a first portion of the time for which the electronic system is operated, and data is stored in a first phase in the memory element for the period of time, and a specific memory element is in a second state for a second portion of the time for which the electronic system is operated, and data is stored in a second phase in the memory element for the period of time.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供使得能够使用场效应晶体管（FET）实现的电子系统能够减少由于偏置温度不稳定性（BTI）导致的阈值电压偏移的方法和装置。 解决方案：当FET处于特定的电压应力状态时，由于BTI引起的VT移位被累积。 电子系统中的许多存储元件在系统的基本寿命内存储相同的数据。 结果，由于BTI引起的VT偏移显着地发生在存储元件中的FET中。 本发明的实施例保证了特定的存储元件在电子系统操作的时间的第一部分处于第一状态，并且数据在存储元件中的第一阶段被存储一段时间， 并且对于电子系统操作的时间的第二部分，特定存储器元件处于第二状态，并且数据被存储在存储元件中的第二阶段一段时间。 版权所有（C）2006，JPO＆NCIPI

    REGULATED SUBSTRATE VOLTAGE GENERATOR
    3.
    发明专利
    REGULATED SUBSTRATE VOLTAGE GENERATOR 未知

    公开(公告)号：DE3379001D1

    公开(公告)日：1989-02-23

    申请号：DE3379001

    申请日：1983-10-26

    Applicant: IBM

    Inventor： DILLINGER THOMAS EDWIN ,  KUEPER TERRANCE WAYNE

    IPC: G05F3/24 ,  G05F3/20 ,  G11C5/14 ,  G11C11/407 ,  H02M3/07 ,  H03K19/094

    Abstract: A regulated on-chip substrate-voltage generator circuit converts a single power supply input and ground potential into a negative potential. The negative potential is applied to the substrate of an integrated circuit upon which the substrate-voltage generator is formed. The substrate voltage generator includes a voltage oscillator connected to a charge pump device. A pair of depletion FETs forms a voltage divider circuit between the ground potential and the substrate potential. An amplifier, formed from depletion FETs, couples the voltage divider into the charge pump. The voltage divider and amplifier regulate the charge pump thereby maintaining tight control over the substrate voltage.

Patent Agency Ranking