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公开(公告)号：BR9101543A
公开(公告)日：1991-12-10
申请号：BR9101543
申请日：1991-04-17
Applicant: IBM
Inventor： DAYAN RICHARD A , LAM SON H , ZIMMERMAN JOHN P
Abstract: An apparatus and method for reclaiming a portion of random access memory in a personal computer system. The personal computer system comprises a system processor, a memory controller, a random access main memory, a read only memory, and at least one direct access storage device. The read only memory includes operating system microcode. The memory controller regulates communications between main memory and the system processor. In response to signals from the system processor, the memory controller can either execute the microcode out of the read only memory and recover main memory previously used to store the microcode, or disable read only memory, copy the microcode to main memory and execute the microcode out of main memory.
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公开(公告)号：CA2052766A1
公开(公告)日：1992-04-27
申请号：CA2052766
申请日：1991-10-04
Applicant: IBM
Inventor： LAM SON H
Abstract: Methods and apparatus for maintaining cache integrity in a computing system that includes a central processing unit (CPU), Random Access Memory (RAM), Read Only Memory (ROM), and a local memory controller for controlling cooperation between said CPU, RAM and ROM, wherein said computing system is capable of supporting a ROM mapped to RAM mode of operation, and further wherein said local memory controller, whenever said ROM mapped to RAM mode is enabled, (1) implements a snoop cycle to detect CPU write ROM operations and, upon detecting such an operation, (2) provides a cache invalidation signal to the CPU. The CPU utilises the invalidation signal, along with the invalidation address on the local bus coupling the CPU and memory controller, to invalidate any cache data entry corresponding to the main memory address targeted by the CPU write ROM operation. The invalidation takes place while the write operation is in progress.
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