-
公开(公告)号：DE2823679A1
公开(公告)日：1979-02-01
申请号：DE2823679
申请日：1978-05-31
Applicant: IBM
Abstract: An array of optically sensitive devices senses printed matter with each device in the array producing an output signal representing a single black or white element in a multi-element picture being sensed by the whole array. These output signals are fed into an analog charge transfer shift register and passed serially in a fixed sequence through an output stage of the shift register. As the signal from each device passes through this output stage the device becomes what is hereafter referred to as the device of interest and the signal produced by it is analyzed to determine whether it is a black or white element. Other output stages simultaneously sense data from devices located around the device of interest to define a subarray within the original detected array while the last of these output stages is fed to a peak comparator to sense the brightest and darkest matter detected in the recent past by any element of the array. The results of these sensings are processed in accordance with a preselected algorithm to generate a digital signal wich is an indication of whether the device of interest has detected black or white.
-
公开(公告)号：GB1301168A
公开(公告)日：1972-12-29
申请号：GB5315570
申请日：1970-11-09
Applicant: IBM
Inventor： LEIGHTON HOWARD NOYES
Abstract: 1301168 Multipliers INTERNATIONAL BUSINESS MACHINES CORP 9 Nov 1970 [26 Feb 1970] 53155/70 Headings G4G and G4H [Also in Division H3] In a digital/analogue multiplier in which the analogue input (e i , Fig. 1, not shown) is passed via resistances R B , R A to first and second input terminals of an operational amplifier having a feedback path connected to the second input terminal, a variable impedance (R V ) controlled by digital signals is connected between the second input terminal and a reference source so that the output (e 0 ) is the product of the input signal (e i ) and the digital signals. In the balanced modulator of Fig. 2 in which R A = R V = R F/2 , binary signals of 0 and 1 at input 20 applied to transistor 26 result in a respective voltage gain of + 0.5 and - 0.5. Circuit 30 may be included to compensate for the offset voltages of transistor 26 and operational amplifier 22 by introducing an offset current at a point 38. In the embodiment of Fig. 3 a nine-bit parallel coded signal is applied to switching transistors Q1-Q9 to connect selected binary weighted resistances R 1 -R 9 between the second input terminal of the operational amplifier and the reference potential.
-
Search Results
2
records
(took 0.018 seconds)
