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公开(公告)号：DE69024842T2
公开(公告)日：1996-08-08
申请号：DE69024842
申请日：1990-04-02
Applicant: IBM
Inventor： GONZALEZ-LOPEZ JORGE , LIANG BOB CHAO-CHU , TANNENBAUM DAVID CONRAD
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公开(公告)号：DE3855214D1
公开(公告)日：1996-05-23
申请号：DE3855214
申请日：1988-10-10
Applicant: IBM
Inventor： LIANG BOB CHAO-CHU
Abstract: A Pipeline and Parallel Processing system for generating Surface Patches for both Wireframe and Solid/Shaded Models in a Raster Graphics Display. The inputs to a Transformation Processor are the parameters for the Rational Bezier Surfaces: a 2-dimensional array of control points, and weights. The outputs are the coordinates of the corner points and the normals (to the surface) of the patches, which make up the surface. The system consists of three Pipeline stages: 1. A front-end processor fetches the data from memory and feeds the Transformation Processor; 2. four Floating Point Processors in Parallel for tessellating the surfaces into small patches; and 3. one Floating Point Processor for generating normals at the vertices of the small patches. The output is sent to the rest of the Graphics System for clipping, mapping, and shading.
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公开(公告)号：DE3788260D1
公开(公告)日：1994-01-05
申请号：DE3788260
申请日：1987-08-18
Applicant: IBM
IPC: G06F7/548 , G06F17/16 , G06T11/00 , G06F15/347 , G06F15/62
Abstract: To avoid the overflow problem, in a graphics display system which employs matrix concatenation for coordinate transformation and matrix element precision equal to that inherent to the system, which can cause an out-of-bounds location of a data element, number translation shift factors are introduced for the last row of the matrix which when used to operate on matrix elements. This will maintain the elements within the physical boundaries of the graphics base by preventing overflow. The disclosed modification can be implemented in microcode in a commercially availably graphics display system such as the IBM 5080 Graphics System.
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Patent Agency Ranking
公开(公告)号：DE3855214T2
公开(公告)日：1996-10-17
申请号：DE3855214
申请日：1988-10-10
Applicant: IBM
Inventor： LIANG BOB CHAO-CHU
Abstract: A Pipeline and Parallel Processing system for generating Surface Patches for both Wireframe and Solid/Shaded Models in a Raster Graphics Display. The inputs to a Transformation Processor are the parameters for the Rational Bezier Surfaces: a 2-dimensional array of control points, and weights. The outputs are the coordinates of the corner points and the normals (to the surface) of the patches, which make up the surface. The system consists of three Pipeline stages: 1. A front-end processor fetches the data from memory and feeds the Transformation Processor; 2. four Floating Point Processors in Parallel for tessellating the surfaces into small patches; and 3. one Floating Point Processor for generating normals at the vertices of the small patches. The output is sent to the rest of the Graphics System for clipping, mapping, and shading.
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公开(公告)号：DE69024842D1
公开(公告)日：1996-02-29
申请号：DE69024842
申请日：1990-04-02
Applicant: IBM
Inventor： GONZALEZ-LOPEZ JORGE , LIANG BOB CHAO-CHU , TANNENBAUM DAVID CONRAD
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公开(公告)号：DE3750784D1
公开(公告)日：1995-01-12
申请号：DE3750784
申请日：1987-03-17
Applicant: IBM
Inventor： LIANG BOB CHAO-CHU , GONZALEZ-LOPEZ JORGE
IPC: G06F3/153 , G06F17/17 , G06T15/80 , G06F15/72 , G06F15/353
Abstract: Method and apparatus are disclosed for providing interpolated display characteristic values, such as intensity or Z value, for pels within a polygon to be displayed by a computer graphics display system. A scanning sequence generates pel addresses such that each pel address so generated is contiguous with a previously generated pel address. The parametric value rate of change in both the X and the Y direction is determined, and expressed as an integer value and a remainder quantity. The remainder quantity is used to determine a sequence, driven by pel address changes, by which the integer parametric value increment from pel to pel is incremented or decremented by one in a regular sequence that assures that the error in the computed parametric value for each pel never exceeds 0.5 parametric value units.
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公开(公告)号：DE3853336T2
公开(公告)日：1995-09-28
申请号：DE3853336
申请日：1988-10-13
Applicant: IBM
Inventor： GONZALEZ-LOPEZ JORGE , HEMPEL BRUCE CARLTON , LIANG BOB CHAO-CHU
Abstract: A lighting model processing system for a computer graphics workstation's shading function includes multiple floating point processing stages arranged and operated in pipeline. Each stage is constructed from one or more identical floating point processors. The lighting model processing system supports one or more light sources illuminating an object to be displayed, with parallel or perspective projection. Dynamic partitioning can be used to balance the computational workload among various of the processors in order to avoid a bottleneck in the pipeline. The high throughput of the pipeline system makes possible the rapid calculation and display of high quality shaded images.
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公开(公告)号：DE3750784T2
公开(公告)日：1995-07-13
申请号：DE3750784
申请日：1987-03-17
Applicant: IBM
Inventor： LIANG BOB CHAO-CHU , GONZALEZ-LOPEZ JORGE
Abstract: Method and apparatus are disclosed for providing interpolated display characteristic values, such as intensity or Z value, for pels within a polygon to be displayed by a computer graphics display system. A scanning sequence generates pel addresses such that each pel address so generated is contiguous with a previously generated pel address. The parametric value rate of change in both the X and the Y direction is determined, and expressed as an integer value and a remainder quantity. The remainder quantity is used to determine a sequence, driven by pel address changes, by which the integer parametric value increment from pel to pel is incremented or decremented by one in a regular sequence that assures that the error in the computed parametric value for each pel never exceeds 0.5 parametric value units.
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