公开(公告)号：JP2005057749A

公开(公告)日：2005-03-03

申请号：JP2004213350

申请日：2004-07-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KING MATTHEW E ,  LIU PEICHUN ,  MUI DAVID ,  QI JIEMING

IPC: H03K17/00 ,  H03K17/62 ,  H04J3/00 ,  H04J3/04

CPC classification number: H04J3/047

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and method for multiplexing a plurality of signals without causing considerable performance deterioration or delay.
SOLUTION: A method is provided for selecting a signal from a plurality of signals. The method includes the steps of (1) providing a plurality of multiplexers, each multiplexer configured to selectively output one of a plurality of input signals inputted by the multiplexer using an output of the multiplexer; (2) selecting an input signal from one of the plurality of multiplexers to output; (3) outputting the selected input signal from the output of the one of the plurality of multiplexers; (4) forcing the outputs of the other of the plurality of multiplexers to a predetermined logic state; and (5) combining the outputs of the plurality of multiplexers so as to output the selected input signal. Numerous other aspects are also provided.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于复用多个信号而不引起相当大的性能劣化或延迟的装置和方法。 解决方案：提供一种用于从多个信号中选择信号的方法。 该方法包括以下步骤：（1）提供多个复用器，每个复用器被配置为使用多路复用器的输出来选择性地输出由多路复用器输入的多个输入信号中的一个; （2）选择来自多个多路复用器中的一个的输入信号来输出; （3）从所述多个复用器中的一个的输出端输出所选择的输入信号; （4）将所述多个复用器中的另一个的输出强制为预定的逻辑状态; 以及（5）组合多个复用器的输出以输出所选择的输入信号。 还提供了许多其他方面。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：AT403905T

公开(公告)日：2008-08-15

申请号：AT05823124

申请日：2005-07-18

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： DAY MICHAEL ,  JOHNS CHARLES ,  LIU PEICHUN ,  TRUONG THUONG ,  YAMAZAKI TAKESHI

IPC: G06F13/28 ,  G06F9/46

Abstract: The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

公开(公告)号：AT373845T

公开(公告)日：2007-10-15

申请号：AT05797447

申请日：2005-07-28

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： KING MATTHEW ,  LIU PEICHUN ,  MUI DAVID ,  YAMAZAKI TAKESHI

IPC: G06F13/28 ,  G06F13/362

Abstract: An apparatus, a method and a computer program are provided for executing Direct Memory Access (DMA) commands. A physical queue is divided into a number of virtual queues by software based on the command type, such as processor to processor, processor to Input/Output (I/O) devices, and processor to external or system memory. Commands are then assigned to a slot based on the type of DMA command: load or store. Once assigned, the commands can be executed by alternating between the slots and by utilizing round robin systems within the slots in order to provide a more efficient manner to execute DMA commands.

公开(公告)号：AT553481T

公开(公告)日：2012-04-15

申请号：AT06755209

申请日：2006-05-16

Applicant: IBM

Inventor： GANFIELD PAUL ,  HASELHORST KENT ,  JOHNS CHARLES ,  LIU PEICHUN

IPC: G11C7/10

Abstract: A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR(TM) DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculation because only 144 of the 256 possible byte values are decoded. The mask value is generated and stored in a mask array. Independently, the write data is stored in a write buffer. The mask value is utilized to generate a write mask command. Once the write mask command is issued, the write data and the mask value are transmitted to a multiplexer. The multiplexer masks the write data using the mask value, so that the masked data can be stored in the XDR DRAMS.

公开(公告)号：AT407403T

公开(公告)日：2008-09-15

申请号：AT05802300

申请日：2005-07-06

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： DAY MICHAEL ,  JOHNS CHARLES ,  LIU PEICHUN ,  TRUONG THUONG ,  YAMAZAKI TAKESHI

IPC: G06F13/28

Abstract: A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.