公开(公告)号：DE69424315D1

公开(公告)日：2000-06-08

申请号：DE69424315

申请日：1994-02-25

Applicant: IBM

Inventor： SCHINDLER RUDOLF ,  LUIJTEN PETER

IPC: G06F12/00 ,  G06F17/30 ,  G11C15/04 ,  H04L49/111 ,  H04Q11/04

Abstract: PCT No. PCT/EP94/00538 Sec. 371 Date Aug. 23, 1996 Sec. 102(e) Date Aug. 23, 1996 PCT Filed Feb. 25, 1994 PCT Pub. No. WO95/23380 PCT Pub. Date Aug. 31, 1995A fast n-bit to k-bit mapping or translation method and apparatus avoiding the use of content addressable memories (CAMs) is described. It essentially is characterized by using two conventional storage (RAMs). In the first storage (3), the n-bit words are stored preferably in an order determined by the binary search key. The second storage (4) holds the corresponding k-bit translations. Both storages are addressed by essentially the same address, which is established during the (binary) search performed to find a match between an input n-bit word and the contents of the first storage. In variants of the invention, the use of parallel comparisons and of pipelining is demonstrated.

公开(公告)号：DE69424315T2

公开(公告)日：2000-11-30

申请号：DE69424315

申请日：1994-02-25

Applicant: IBM

Inventor： SCHINDLER RUDOLF ,  LUIJTEN PETER

IPC: G06F12/00 ,  G06F17/30 ,  G11C15/04 ,  H04L49/111 ,  H04Q11/04

Abstract: PCT No. PCT/EP94/00538 Sec. 371 Date Aug. 23, 1996 Sec. 102(e) Date Aug. 23, 1996 PCT Filed Feb. 25, 1994 PCT Pub. No. WO95/23380 PCT Pub. Date Aug. 31, 1995A fast n-bit to k-bit mapping or translation method and apparatus avoiding the use of content addressable memories (CAMs) is described. It essentially is characterized by using two conventional storage (RAMs). In the first storage (3), the n-bit words are stored preferably in an order determined by the binary search key. The second storage (4) holds the corresponding k-bit translations. Both storages are addressed by essentially the same address, which is established during the (binary) search performed to find a match between an input n-bit word and the contents of the first storage. In variants of the invention, the use of parallel comparisons and of pipelining is demonstrated.

公开(公告)号：DE69518545D1

公开(公告)日：2000-09-28

申请号：DE69518545

申请日：1995-01-26

Applicant: IBM

Inventor： LUIJTEN PETER ,  WEBB JOHN

IPC: H04Q3/00 ,  H04L12/28 ,  H04L49/111 ,  H04Q11/04

Abstract: PCT No. PCT/EP95/00276 Sec. 371 Date Jul. 7, 1997 Sec. 102(e) Date Jul. 7, 1997 PCT Filed Jan. 26, 1995 PCT Pub. No. WO96/23391 PCT Pub. Date Aug. 1, 1996A switch for use in an ATM network is disclosed. The switch is designed to perform a function beyond that normally achievable with a virtual path switch functioning in accordance with the ATM standard. The switch according to the invention has data stored in a look-up table (431-433) which allows it to identify communication cells of particular individual virtual channels, indicated by the virtual path identifier (VCI), although these cells cannot be distinguished on the basis of their virtual path indicators (VPIs). This identification is attempted before the usual step of forwarding an incoming communication cell based solely on its virtual path indicator. A priority circuitry (44) ensures that entries associated with the combined VPI/VCI is given a priority over those associated only with the VPI. The switch can extract cells of individual virtual channels passing through it. It can also insert virtual channels into the ATM network.