公开(公告)号：SG100751A1

公开(公告)日：2003-12-26

申请号：SG200105184

申请日：2001-08-24

Applicant: IBM

Inventor： GORDON TAYLOR DAVIS ,  MARCO C HEDDES ,  ROSS BOYD LEAVENS ,  MARK ANTHONY RINALDI

IPC: G06F9/38 ,  G06F9/46 ,  G06F13/10 ,  G06F13/14 ,  G06F15/00 ,  G06F15/16 ,  G06F15/163 ,  G06F15/76 ,  G06F15/78 ,  G06F15/80 ,  H04L29/06

Abstract: An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.