公开(公告)号：JP2002149424A

公开(公告)日：2002-05-24

申请号：JP2001265792

申请日：2001-09-03

Applicant: IBM

Inventor： DAVIS GORDON TAYLOR ,  MARKO C HEADS ,  RIWENS ROSE BOYED ,  RINALDI MARK ANTHONY

IPC: G06F9/38 ,  G06F9/46 ,  G06F13/10 ,  G06F13/14 ,  G06F15/00 ,  G06F15/16 ,  G06F15/163 ,  G06F15/76 ,  G06F15/78 ,  G06F15/80 ,  H04L29/06

Abstract: PROBLEM TO BE SOLVED: To increase the communicating efficiency of a protocol processor unit(PPU) and a coprocessor in a network processor. SOLUTION: An integrated processor composite body is provided with a plurality of protocol processor units(PPU). The respective units are provided with at least one or preferentially two individually functioning core language processors(CLP). The respective CLP are allowed to support dual threads through a logical coprocessor execution/data interface with a plurality of exclusive coprocessors to be used for the respective PPU. In response to an operation instruction, the PPU identifies an events whose waiting time is long and an event whose waiting time is short, and controls and switches the priority order of the execution of threads based on the identification. Also, in response to the operation instruction, the conditional execution of the specific coprocessor operation is made available when the designated specific event is generated or not generated.