公开(公告)号：FR2276694A1

公开(公告)日：1976-01-23

申请号：FR7424577

申请日：1974-06-28

Applicant: IBM FRANCE

Inventor： MARZIN CLAUDE ,  ROUGEAUX CLAUDE ,  VERNES PATRICE

IPC: H03K19/21 ,  H01L27/092 ,  H03K19/096 ,  H01L27/06 ,  H03K19/32

公开(公告)号：DE2965749D1

公开(公告)日：1983-07-28

申请号：DE2965749

申请日：1979-10-12

Applicant: IBM

Inventor： BERANGER HERVE LEONARD ,  MARZIN CLAUDE ,  OMET DOMINIQUE MARCEL ,  PETER JEAN-LUC

IPC: H02J1/00 ,  G05F3/22 ,  G06F1/26 ,  G06F12/16 ,  G11C11/41 ,  G11C11/411 ,  G11C11/413 ,  G11C11/415 ,  G11C11/40 ,  G05F3/20 ,  G11C8/00

公开(公告)号：FR2296969A1

公开(公告)日：1976-07-30

申请号：FR7443620

申请日：1974-12-31

Applicant: IBM FRANCE

Inventor： GAUTIER YVES ,  MARZIN CLAUDE

IPC: G06F11/10 ,  H03K19/0948 ,  H03K19/21 ,  H03K19/32

Abstract: The 3 x 3 bit parity checking circuit, for 8 bit blocks, has only four logic circuits each constructed using CMOS-techniques. These four CMOS logic circuits are identical XOR gates (21-24). Each of three of these gates is connected to 3 of the nine input bits (8 data bits + 1 parity bit (A9)). The outputs of these three gates are passed to the 3 inputs of the fourth gate. The advantage of this parity checking circuit lies in its using only four logic gates and in constructing these using CMOS elements.

公开(公告)号：FR2296966A1

公开(公告)日：1976-07-30

申请号：FR7443621

申请日：1974-12-31

Applicant: IBM FRANCE

Inventor： GAUTIER YVES ,  MARZIN CLAUDE

IPC: G06F7/02 ,  H03K19/0948 ,  H03K19/08

Abstract: The 2 x 2 bit CMOS comparator, for comparing two words each of 8 data bits and 1 parity bit, compares the homologous bits (one from each word) in pairs using XOR gates which give output changes when two homologous bits are the same - ie all gates have given output states when the two words are identical. The comparator consists of identical cells each comparing two words of two bits and constructed using fewer MOSFETs than similar existing types of circuit. The switching delay is also reduced so too is the parasitic capacitance. The design allows high packing densities.