公开(公告)号：CA1244141A

公开(公告)日：1988-11-01

申请号：CA498869

申请日：1986-01-02

Applicant: IBM

Inventor： BLEVINS BALLARD J ,  KULPA WILLIAM G ,  MATHIS JOSEPH R ,  MCCULLOUGH JOHN W

IPC: G06F13/36 ,  G06F12/06 ,  G06G7/02

Abstract: BUS TO BUS TRANSLATION The present invention relates to data processing systems having a central processing unit and a global storage unit connected by a system bus, and an I/O bus which is connected to the system bus by means of a bus converter. Selected I/O devices are randomly attached to the I/O bus. The present invention provides a programmable bus converter which dynamically inserts appropriate address control information into messages transmitted from the I/O bus to the system bus. In one preferred embodiment of the present invention the bus converter is provided with means whereby access can be denied to and from selected I/O devices.

公开(公告)号：FR2374792A1

公开(公告)日：1978-07-13

申请号：FR7733126

申请日：1977-10-27

Applicant: IBM

Inventor： MATHIS JOSEPH R

IPC: G04F3/00 ,  G04F10/00 ,  G04F10/04 ,  G05B19/02 ,  G06F11/30 ,  G06F13/00 ,  G06F13/37 ,  G06F13/42 ,  H04Q9/00 ,  H04L7/04

Abstract: A composite shift register timer for controlling a sequence of events occurring over a demand-response interface. The composite shift register comprises a primary shift register and a secondary shift register. The primary shift register is divided into successive portions which are selectively coupled together in successive pairs upon timely receipt of respective response signals. A first binary "1" is inserted into the first portion at the start of a predetermined sequence of events. The first "1" is clocked through to the end of the first portion where it initiates a demand and is stored pending the receipt of a corresponding response. A second binary "1" is clocked through the secondary shift register beginning with the initiation of each demand. The clocking of the second "1" continues until the receipt of a timely response to the initiated demand whereupon the secondary shift register is reset. The timely response also is applied to the coupling means between the first and second portions of the primary shift register to permit the stored first "1" to propagate into and be clocked through the second portion. If no timely response is received, the second "1" propagates to the end of the secondary shift register to produce an "error" signal. The error signal deactivates each coupling means between the portions of the first shift register to prevent the first binary "1" from propagating any farther, thus terminating the sequence of events.