公开(公告)号：CA1236588A

公开(公告)日：1988-05-10

申请号：CA491267

申请日：1985-09-20

Applicant: IBM

Inventor： BRANTLEY WILLIAM C JR ,  MCAULIFFE KEVIN P ,  NORTON VERN A ,  PFISTER GREGORY F ,  WEISS JOSEPH

IPC: G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F15/17

Abstract: Method and Apparatus for dynamically partitioning a storage system into a global storage efficiently accessible by a number of processors connected to a network, and local storage efficiently accessible by individual processors, including means for interleaving storage references by a processor; means under the control of each processor for controlling the means for interleaving storage references and means for dynamically directing storage references to first or second portions of storage.

公开(公告)号：CA2062910A1

公开(公告)日：1992-11-24

申请号：CA2062910

申请日：1992-03-12

Applicant: IBM

Inventor： BAYLOR SANDRA J ,  MCAULIFFE KEVIN P ,  RATHI BHARAT D

IPC: G06F12/08 ,  G06F15/16 ,  G06F15/177

公开(公告)号：CA2062910C

公开(公告)日：1998-09-22

申请号：CA2062910

申请日：1992-03-12

Applicant: IBM

Inventor： BAYLOR SANDRA J ,  MCAULIFFE KEVIN P ,  RATHI BHARAT D

IPC: G06F12/08 ,  G06F15/16 ,  G06F15/177

Abstract: A directory-based protocol is provided for maintaining data coherency in a multiprocessing (MP) system having a number of processors with associated write-back caches, a multistage interconnection network (MIN) leading to a shared memory, and a global directory associated with the main memory to keep track of state and control information of cache lines. Upon a request by a requesting cache for a cache line which has been exclusively modified by a source cache, two buffers are situated in the global directory to collectively intercept modified data words of the modified cache line during the write-back to memory. A modified word buffer is used to capture modified words within the modified cache line. Moreover, a line buffer stores an old cache line transferred from the memory, during the write back operation. Finally, the line buffer and the modified word buffer, together, provide the entire modified line to a requesting cache.

公开(公告)号：CA1311851C

公开(公告)日：1992-12-22

申请号：CA589107

申请日：1989-01-25

Applicant: IBM

Inventor： MCAULIFFE KEVIN P ,  NORTON VERN A ,  PFISTER GREGORY F ,  RATHI BHARAT D

IPC: G06F15/167 ,  G06F12/12 ,  G06F13/16 ,  G06F15/173 ,  H04L12/56 ,  G06F15/16

Abstract: Y0986-112 A HARDWARE MECHANISM FOR AUTOMATICALLY DETECTING HOT-SPOT REFERENCES AND DIVERTING SAME FROM FROM MEMORY TRAFFIC IN A MULTIPROCESSOR COMPUTER SYSTEM An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks are provided each capable of interconnecting any processor to any memory module, and each having different latency characteristics. A Hot-Spot detection means is associated with each main memory module for detecting when a particular address in that module has become a Hot Spot and includes a first memory for storing all detected Hot Spots. A diverter element is associated with each processor for selectively routing memory requests over either said first or second memory network contingent on its status as a Hot Spot. A second memory is included in each diverter element for storing all Hot Spots detected by the detector elements. A control mechanism determines if any current main memory address is a listed Hot Spot within said second memory and, if so, causes the main memory reference to be transmitted to the memory system over a selected interconnection network. Another component of this mechanism determines if a Y0986-112 particular address has been accessed a sufficient number of times within a given timeframe to be deemed a Hot Spot and removes Hot Spots from both the first and second memories when necessary.