-
1.发明专利
公开(公告)号：NZ235002A
公开(公告)日：1992-08-26
申请号：NZ23500290
申请日：1990-08-21
Applicant: IBM
Abstract: A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory (106,112) which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements (104,116) on the pipe which represent requests, replies, and status information. The units (622,624) send and receive control elements (104,116) independent of the other units which allows free flowing asynchronous delivery of control information and data between units (622,624). The shared memory (106,112) can be organised as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements (104,116) and the other pipe for inbound control elements (104,116). The control elements (104,116) have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.
-
2.发明专利
公开(公告)号：CA2025711C
公开(公告)日：1998-03-31
申请号：CA2025711
申请日：1990-09-19
Applicant: IBM
Abstract: A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements on the pipe which represent requests, replies, and status information. The units send and receive control elements independent of the other units which allows free flowing asynchronous delivery of control information and data between units. The shared memory can be organized as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements and the other pipe for inbound control elements. The control elements have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.
-
公开(公告)号：SG44433A1
公开(公告)日：1997-12-19
申请号：SG1996000367
申请日：1990-08-30
Applicant: IBM
Abstract: A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory (106,112) which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements (104,116) on the pipe which represent requests, replies, and status information. The units (622,624) send and receive control elements (104,116) independent of the other units which allows free flowing asynchronous delivery of control information and data between units (622,624). The shared memory (106,112) can be organised as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements (104,116) and the other pipe for inbound control elements (104,116). The control elements (104,116) have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.
-
Patent Agency Ranking
-
5.发明专利
公开(公告)号：AU630493B2
公开(公告)日：1992-10-29
申请号：AU6130990
申请日：1990-08-24
Applicant: IBM
Abstract: A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory (106,112) which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements (104,116) on the pipe which represent requests, replies, and status information. The units (622,624) send and receive control elements (104,116) independent of the other units which allows free flowing asynchronous delivery of control information and data between units (622,624). The shared memory (106,112) can be organised as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements (104,116) and the other pipe for inbound control elements (104,116). The control elements (104,116) have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.
-
公开(公告)号：BR9004685A
公开(公告)日：1991-09-10
申请号：BR9004685
申请日：1990-09-20
Applicant: IBM
Inventor： BONAVENTO FRANCIS M , MCGOVERN JOSEPH PATRICK , THOMAS EUGENE M
Abstract: A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory (106,112) which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements (104,116) on the pipe which represent requests, replies, and status information. The units (622,624) send and receive control elements (104,116) independent of the other units which allows free flowing asynchronous delivery of control information and data between units (622,624). The shared memory (106,112) can be organised as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements (104,116) and the other pipe for inbound control elements (104,116). The control elements (104,116) have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.
-
7.发明专利
公开(公告)号：AU6130990A
公开(公告)日：1991-03-28
申请号：AU6130990
申请日：1990-08-24
Applicant: IBM
Abstract: A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory (106,112) which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements (104,116) on the pipe which represent requests, replies, and status information. The units (622,624) send and receive control elements (104,116) independent of the other units which allows free flowing asynchronous delivery of control information and data between units (622,624). The shared memory (106,112) can be organised as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements (104,116) and the other pipe for inbound control elements (104,116). The control elements (104,116) have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.
-
公开(公告)号：PH30203A
公开(公告)日：1997-02-05
申请号：PH41067
申请日：1990-08-22
Applicant: IBM
Abstract: A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory (106,112) which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements (104,116) on the pipe which represent requests, replies, and status information. The units (622,624) send and receive control elements (104,116) independent of the other units which allows free flowing asynchronous delivery of control information and data between units (622,624). The shared memory (106,112) can be organised as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements (104,116) and the other pipe for inbound control elements (104,116). The control elements (104,116) have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.018 seconds)
