公开(公告)号：GB2573239A

公开(公告)日：2019-10-30

申请号：GB201911402

申请日：2018-01-08

Applicant: IBM

Inventor： MICHAEL KLAUS KROENER ,  UDO KRAUTZ ,  TINA BABINSKY ,  SILVIA MELITTA MUELLER ,  ANDREAS WAGNER

IPC: G06F7/483 ,  G06F7/544

Abstract: A floating-point unit (10), being configured to implement a fused-multiply-add operation on three 128 bit wide operands (100, 102, 104), comprising: (i) a 113×113-bit multiplier (14); (ii) a left shifter (18); (iii) a right shifter (20); (iv) a select circuit (24) comprising a 3-to-2 compressor (25); (v) an adder (26) connected to the dataflow from the select circuit (24); (vi) a first feedback path (36) connecting a carry output (91) of the adder (26) to the select circuit (24); (vii) a second feedback path (38) connecting the output of the adder (26) to the shifters (18, 20) for passing an intermediate wide result (86) through the shifters (18, 20).

公开(公告)号：GB2573239B

公开(公告)日：2020-03-04

申请号：GB201911402

申请日：2018-01-08

Applicant: IBM

Inventor： MICHAEL KLAUS KROENER ,  UDO KRAUTZ ,  TINA BABINSKY ,  SILVIA MELITTA MUELLER ,  ANDREAS WAGNER

IPC: G06F7/483 ,  G06F7/544

Abstract: A floating-point unit, configured to implement a fused-multiply-add operation on three 128 bit wide operands is provided, which includes a 113×113-bit multiplier; a left shifter; a right shifter; a select circuit including a 3-to-2 compressor; an adder connected to the dataflow from the select circuit; a first feedback path connecting a carry output of the adder to the select circuit; a second feedback path connecting the output of the adder to the shifters for passing an intermediate wide result through the shifters.