公开(公告)号：GB2347016A

公开(公告)日：2000-08-23

申请号：GB0001002

申请日：2000-01-18

Applicant: IBM

Inventor： LAM CHUNG HON ,  MILES GLEN ,  NAKOS JAMES SPIROS ,  WILLETS CHRISTA

IPC: H01L21/8238 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8239

Abstract: An integrated circuit comprises a non-volatile random access memory (NVRAM) array with gates formed in three polysilicon conductive layers 134, 144, 158. The first conductive layer 134 forms the floating gate of an EEPROM cell 122, and the second layer 144 forms wordlines 180, 182 and gates of high voltage (access) FETs 118, 120. Gates of logic FETs 114, 116 are formed from the third conductive layer 158. The third conductive layer may be used as a mask for the wordlines and high voltage gates.

公开(公告)号：GB2347016B

公开(公告)日：2003-07-02

申请号：GB0001002

申请日：2000-01-18

Applicant: IBM

Inventor： LAM CHUNG HON ,  MILES GLEN ,  NAKOS JAMES SPIROS ,  WILLETS CHRISTA

IPC: H01L21/8238 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8239

Abstract: A logic chip including a non-volatile random access memory (NVRAM) array and method of fabrication thereof. The chip includes devices with gates on one or more of three polysilicon layers. Chip logic uses normal FETs and array support includes high voltage FETs. Both logic and support are CMOS. The gates of normal FETs in the chip logic are from the third, uppermost polysilicon layer. The third poly silicon layer also is used as a mask for high voltage FETs and array word lines, both of which use the second polysilicon layer for gates. The first polysilicon layer is used solely for cell floating gates.