公开(公告)号：CA922810A

公开(公告)日：1973-03-13

申请号：CA94172

申请日：1970-09-28

Applicant: IBM

Inventor： JONES J W ,  MINSHULL J F ,  HALLETT M H ,  GARDNER P L ,  FLINDERS M

IPC: G11C15/00 ,  G11C15/04 ,  G11C29/00 ,  G11C29/04

公开(公告)号：AU511040B2

公开(公告)日：1980-07-24

申请号：AU3165977

申请日：1977-12-16

Applicant: IBM

Inventor： EVANS J M ,  JUDD I D ,  LOVIE R H ,  MINSHULL J F

IPC: H04N5/262 ,  G06K9/54 ,  G06T3/00 ,  G06T9/20 ,  G06T11/20 ,  G09G5/36 ,  H04N1/411 ,  H04N1/02 ,  H04N1/04

Abstract: Graphical data on a document is raster scanned and the resulting bit pattern is processed to provide a processed bit pattern which represents lines which each are a single pel in width and indicative of the shapes of objects scanned on the document. These single pel wide lines may represent the outlines of objects on the center lines. The processed bit pattern is then directed to a line follower in which bits representing contiguous pels are detected and tested for linearity. When contiguous pels fail the linearity test, a new vector is started and the vector being tracked is terminated. Hardware for performing these operations is described. The resulting vector list is stored until needed for display. Optionally a display station can be used to correct faulty vectors or to encode alphanumeric data in a more convenient format than vector coding.

公开(公告)号：BE748547A

公开(公告)日：1970-09-16

申请号：BE748547D

申请日：1970-04-06

Applicant: IBM

Inventor： ARULPRAGASAM J A ,  LLEWELYN R J ,  MINSHULL J F ,  PERRY L

IPC: G11C15/00 ,  G11C15/04 ,  G11C

公开(公告)号：AU508981B2

公开(公告)日：1980-04-17

申请号：AU3161477

申请日：1977-12-15

Applicant: IBM

Inventor： JUDD I D ,  MINSHULL J F

IPC: G06F3/12 ,  G06K9/54 ,  G06T3/00 ,  G06T9/20 ,  G09G5/24 ,  H04N1/04

Abstract: 1517869 Image encoding apparatus INTERNATIONAL BUSINESS MACHINES CORP 20 Dec 1976 53034/76 Heading H4P Data in the form of a stream of bits representing picture elements (pels), derived from the raster scanning of a document 1, is stored in compressed form in a store 8 which can be accessed so that the data pertaining to the stored document can be transmitted to a receiver 13 or can be expanded in a decompressor 9 for plotting or printing by a plotter 10 or for display on a display unit. The required compression is effected by passing the original bit stream through a pel stripper 3 where bits are removed to leave a processed bit pattern in which the bits represent predominantly single-pel-width strokes constituting either the outlines or the centre lines of characters. A segment follower 6 detects contiguous bits and produces a series of segments representing the tracked strokes. Each segment is coded in an encoder 7 into code words representing the shape of the segments and code words representing the end points of the segments, the segment bit thus produced being stored in the store 8. The stripping process is described with reference to Fig. 2 (not shown), whilst the constraints which determine whether a pel is or is not stripped from the original bit stream are described with reference to Figs. 5 and 6 (not shown). Suitable arrangements for the units 3, 6 and 7 are described with reference to Figs. 7 to 13 (not shown).

公开(公告)号：BE762664A

公开(公告)日：1971-07-16

申请号：BE762664

申请日：1971-02-08

Applicant: IBM

Inventor： ARULPRAGASAM J A ,  MINSHULL J F ,  MURPHY A S

IPC: G06F13/12 ,  G11C15/04 ,  G06F

Abstract: A multiplex input/output (I/O) channel in which channel functions are carried out by associative stores. Three associative stores are used, a control store, an address store and a data store. The data store acts as a data buffer store and also handles most of the interchange of control signals between the channel and the I/O control units. Tag-in I/O signals are used directly as keys in table look-up on interface response tables and initiate the appropriate response from the channel. The address store assemblies the main store address and is also responsible for some of the tag-out I/O signals. Subchannels are allotted only when they are needed. There are a limited number of subchannel areas and these are marked when they are allotted to control units. An extra marker identifies the subchannel currently in use. Any control unit can be allotted to any subchannel.

公开(公告)号：BE748548A

公开(公告)日：1970-09-16

申请号：BE748548D

申请日：1970-04-06

Applicant: IBM

Inventor： FLINDERS B ,  GARDNER P L ,  HALLETT M H ,  JONES J W ,  MINSHULL J F ,  TAYLOR K G

IPC: G06F12/16 ,  G06F11/16 ,  G11C15/04 ,  G06F

Abstract: 1,265,013. Electric digital data storage: computers. INTERNATIONAL BUSINESS MACHINES CORP. 24 April, 1969, No. 20902/69. Headings G4A and G4C. Error detecting circuitry checks data transfer between two registers to provide an error signal only in the absence of a bit of one value in any order of the second register when the same order of the first register contains a bit of the one value. In Fig. 1 two associative stores 1, 2 storing the same information have a selector trigger 4 (to indicate match) for each word location 3, and each have two input/output registers 12, 13 for store 1 and 15, 16 for store 2. Register 13 can also feed and be fed by a bus 23, register 16 can be fed by bus 23, register 12 can be fed by a bus 24, and register 15 can feed and be fed by bus 24, via drivers 26, 30 and receivers 25, 26, 28, 29. One or more further pairs of associative stores may be connected to the buses 23, 24 as may non-associative stores, and the buses communicate with each other via a buffer which may be in the main memory of a computer system using the invention or may be a single separate register. Error features.-During simultaneous associative search in stores 1 and 2 using the same search argument from registers 12, 15 or 13, 16, comparators 6 produce an error signal if different selector triggers 4 are set by the two stores. After read, comparators 18 produce an error signal if input/output registers 12 and 15, or 13 and 16, have unequal contents (only one pair of registers is loaded from the store). Following this, to transfer out the read information and prepare for the next associative search, registers 13, 15 are gated (by actuating drivers 26, 30) to buses 23, 24 respectively, the buses being gated (by actuating receivers 27, 28) to registers 16, 12 almost immediately afterwards. An error signal is now produced unless there is a 1 in register 12 for each 1 in register 15 and a 1 in register 16 for each 1 in register 13 (this form of check being used since other stores may be using the buses simultaneously so a simple equal/unequal check cannot be used). Parity circuits 31, 33 connected in series, generate the parity of the data being supplied to registers 12, 16 from the buses 24, 23 (see above) and this parity is compared (not shown) with parity generated for the data on the buses by two parity circuits (not shown) connected to the respective buses and in series with each other, an error signal being produced on inequality. The buses 23, 24 are now gated (by actuating receivers 25, 29) to the registers 13, 15. An error signal is produced if registers 12 and 15, or 13 and 16, are now unequal as determined by comparators 18. After a write operation, all the receivers are actuated to load registers 12, 13, 15, 16 from the buses for the next associative search, parity checking, and an inequality check by 18, being done as above. After associative interrogation, an extra check on the drivers 26, 30 is done by inhibiting all drivers (of all pairs of stores linked to the buses) and generating the parity of the data on the buses, an error signal being produced if it is non-zero. Detection of any error causes retry (repetitive) of the storage cycle giving the error. If this is unsuccessful and the error can be attributed to data errors, an incorrect word is replaced by its duplicate from the other store 1 or 2 followed by retry. If still unsuccessful, or if the error cannot be attributed to data errors, lines 42, 43 are de-energized to isolate the pair of stores from the buses. If the error signal came from mismatched selector triggers 4, the selector triggers are reset (their states having been saved in a diagnostic column of each store 1, 2), then set in turn by a " next " operation which causes a 1 to shift down each column of triggers 4. If the is do not arrive at the bottoms of the columns simultaneously (even after retires) the the stores are isolated from the buses. If they do arrive simultaneously a read operation is performed and if comparators 18 (which should be comparing zeroes) detect inequality, the selector triggers 4 are not resetting properly, so the stores are isolated from the buses. If this does not happen, the " next " operation is good, and is used repeatedly to read out successive bits of the diagnostic columns for comparison at 18, inequality causing the rest of the words corresponding to the unequal diagnostic column bits to be read out for parity checks (by means not shown). If both words have correct parity, the stores are isolated, but if only one is correct, the incorrect word is replaced by the correct one via the two buses. Fig. 6 (not shown) shows two stages of a parity circuit having a stage for each bit position of a word whose parity is to be generated. A typical stage comprises a transistor tree controlled by a parity input in true and complement form from the preceding stage, and by the corresponding bit of the word, to produce a parity output in true and complement form to the next stage. The circuit can also be used for checking parity. Fig. 7 (not shown) shows one stage of a comparator, having outputs indicating (A and not B), (B and not A) respectively, where A, B are the bits being compared. Both outputs are sensed for the inequality comparison and only one for the ones comparison above.