公开(公告)号：CA1092664A

公开(公告)日：1980-12-30

申请号：CA278844

申请日：1977-05-20

Applicant: IBM

Inventor： MITCHELL RALPH C ,  PI SHING-CHOU ,  LONG GERALD B

IPC: H01L27/112 ,  H03K19/177 ,  G11C11/40 ,  H03K19/08

Abstract: TIME SHARED PROGRAMMABLE LOGIC ARRAY This specification describes arrays for performing logic functions. In these arrays input variables are placed on a series of parallel input lines that intersect a number of parallel output lines in a grid of intersections, Field effect devices at these intersections have their gate terminals connected to one of the input lines and their source terminal connected to one of the output lines and through a load device to a source of potential. The drain terminals of these devices are either unconnected, connected directly to ground or connected to ground through one of two switching devices. The devices with unconnected drains are inoperative. The devices with their drains connected directly to ground are operative at all times. While the devices connected to ground through one of the switches are operative only when the switch is closed. The array can be time shared by two different logic functions by having one or the other of the switches off at any given time.

公开(公告)号：FR2357112A1

公开(公告)日：1978-01-27

申请号：FR7716237

申请日：1977-05-23

Applicant: IBM

Inventor： MITCHELL RALPH C ,  PI SHING C ,  LONG GERALD BERNARD

IPC: H01L27/112 ,  H03K19/177 ,  H03K19/08

Abstract: 1523859 Logic INTERNATIONAL BUSINESS MACHINES CORP 18 May 1977 [30 June 1976] 20896/77 Heading G4H In a logic-performing matrix of devices (e.g. FETs), with orthogonal input and output conductors, first and second groups of the devices are coupled to a source of operating potential in respective first and second states of switching means. The two states are used at different times and select different logic functions to be performed. A first such matrix (AND) may feed another such (OR), and integrated circuitry may be used.