公开(公告)号：JP2009110299A

公开(公告)日：2009-05-21

申请号：JP2007282322

申请日：2007-10-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KAWAHITO MOTOHIRO ,  MORIYAMA TAKAO ,  KOMATSU HIDEAKI

IPC: G06F9/45

CPC classification number: G06F8/443 ,  G06F8/4435

Abstract: PROBLEM TO BE SOLVED: To optimize a process calculating a value to be assigned to a variable. SOLUTION: A compiler apparatus for optimizing a program includes: a range analysis unit for analyzing a range of a value assignable to the variable by the instruction, as a range of the variable in the case where the instruction is executed in terms of an instruction to assign a value to a variable in the program; a determination unit for determining if the execution result of the program does not change even if the instruction assigns any value in the range of the variable on the basis of the analyzed range of the variable; and a replacement unit for replacing the instruction to assign the value to the variable with an instruction to assign a constant value in the range of the variable to the variable on condition that the determination by the determination unit is formed. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：优化计算要分配给变量的值的过程。 解决方案：用于优化程序的编译装置包括：范围分析单元，用于通过指令分析可分配给该变量的值的范围，作为在执行指令的情况下的变量的范围 为程序中的变量分配值的指令; 确定单元，用于确定程序的执行结果是否不改变，即使该指令基于变量的分析范围分配变量范围中的任何值; 以及替换单元，用于在形成由确定单元的确定的条件下，用用于将变量的范围中的常数值分配给变量的指令来替换指定值以赋值给变量的指令。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2002312155A

公开(公告)日：2002-10-25

申请号：JP2001107700

申请日：2001-04-05

Applicant: IBM

Inventor： MORIYAMA TAKAO ,  KAWASE KATSURA

IPC: G06F3/153 ,  G09G5/00 ,  H04W84/12 ,  H04W92/08 ,  H04Q7/38

Abstract: PROBLEM TO BE SOLVED: To smoothly switch between a wire connection and a wireless connection, when a system is equipped with a wire connection channel and with a wireless connection channel between the system and a terminal. SOLUTION: Communication between a display device 50 and an arithmetic processing unit (host) 10 is provided with two connection modes, a wire connection mode for communication via the wire connection channel 20 and a wireless connection mode for communication via the wireless connection channel 30. Before entering the wireless connection mode, the processing unit (host) 10 sends out information needed for the wireless connection from/to the display device 50 via the connection channel 30 and information necessary for authentication for allowing access of information, using the connection channel 30 to the display device 50 via the connection channel 20.

公开(公告)号：JP2000057329A

公开(公告)日：2000-02-25

申请号：JP21885298

申请日：1998-08-03

Applicant: IBM

Inventor： KAWASE KATSURA ,  MORIYAMA TAKAO ,  NAKAMURA HIDEFUMI

IPC: G06F15/16 ,  G06F9/50 ,  G06F15/177 ,  G06F15/80 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To draw out the performance of a whole system as much as possible by detecting the increase/decrease of a feature variable in a quene for transmitting/receiving processed results between plural groups and changing the allotment of processing in the respective groups based on the increase/ decrease of the feature variable. SOLUTION: A processing allotment controller 11 monitors command queues 1 (7), 2 (9) and detects the increase/decrease of a feature variable to be an index in the case of changing the processing allotment. When the feature variable of the command quene 1 (7) is reduced to more than a prescribed threshold, the controller 11 instructs a processor group 1 (1) to execute only a process 0 and instructs a processor group 2 (3) also to execute a process 1. When the feature variable of the command queue 2 (9) is reduced to more than the prescribed threshold, the allotment processes are adjusted between both processor groups 2 (3) and 3 (5).

公开(公告)号：JPH11331610A

公开(公告)日：1999-11-30

申请号：JP11909298

申请日：1998-04-28

Applicant: IBM

Inventor： KAWASE KATSURA ,  MORIYAMA TAKAO ,  NAKAMURA HIDEFUMI

IPC: G06F3/153 ,  G06F13/00 ,  G06T1/60 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  H04N1/41 ,  H04N7/18

Abstract: PROBLEM TO BE SOLVED: To transmit picture information with high resolution even with the small band width of a transmission path by transmitting information of respective pixels in each block in order of the values of corresponding matrix elements in a dither matrix. SOLUTION: CPU 7 executes a processing by using a main memory 9. A plotting instruction is outputted to a plotting controller 11 at the time of plotting in the display 27 of a monitor 3. The plotting controller 11 reads required data from a frame memory 1(15) and writes data in the frame memory 1(15). A transfer controller 19 outputs data of the pixel in the frame memory 1(15) to the monitor 3 with a transmission path 5. In this case, a dirty bit memory 17 is referred. Then, the plural pixels in the frame memory 1(15) are divided into the plural blocks by the size of the dither matrix and corresponding pixel data are transmitted in order of the values of the matrix elements of the dither matrix in the blocks.

公开(公告)号：JPH0793266A

公开(公告)日：1995-04-07

申请号：JP21243293

申请日：1993-08-27

Applicant: IBM

Inventor： KAWASE KATSURA ,  MORIYAMA TAKAO ,  ONO MAKOTO

IPC: G06F9/46 ,  G06F9/50 ,  G06T1/20 ,  G06T11/00 ,  G06F15/16

Abstract: PURPOSE: To parallelly perform processing in multiple processors by quickly utilizing a TSL snapshot at an optional point of time and making a graphic system to efficiently allocate a plotting instruction to respective nodes. CONSTITUTION: When an attribute setting instruction is sent out, it is written in a first TSL buffer first. At the time, a difference between the corresponding addresses of first and second TSL buffers is obtained by a comparator circuit and a change part is stored by a TAG circuit. In the meantime, when a primitive is allocated, the contents of the TAG circuit is referred to and copying is performed from the first TSL buffer to the second TSL buffer only for the change part. Then, the second TSL buffer is locked and the instantaneous value of the TSL is held. An MPU performs a plotting processing while referring to the snapshot of the TSL held by the second TSL buffer.

公开(公告)号：JP2009182605A

公开(公告)日：2009-08-13

申请号：JP2008019281

申请日：2008-01-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： INOUE HIROSHI ,  MORIYAMA TAKAO

IPC: H04N19/50 ,  H04N7/32 ,  H04N19/20 ,  H04N19/503 ,  H04N19/51 ,  H04N19/543 ,  H04N19/61 ,  H04N19/625 ,  H04N19/91

CPC classification number: H04N19/543 ,  H04N19/162 ,  H04N19/527 ,  H04N19/61

Abstract: PROBLEM TO BE SOLVED: To compute an accurate motion vector at a small amount of calculation. SOLUTION: In a system for compressing a moving picture image obtained by projecting a three-dimensional object moving relative to a screen inside a three-dimensional space on the screen, there is provided the system which comprises: a motion computing part for projecting a motion inside the three-dimensional space of the object between a time corresponding to a compression target frame and a time corresponding to the other frames on the screen to compute the motion vector inside the screen of the object; and a compression part for compressing the compression target frame by a motion compensation based on the motion vector. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：以少量的计算来计算精确的运动矢量。 解决方案：在用于压缩通过投影相对于屏幕内的三维空间内的屏幕移动的三维对象而获得的运动图像图像的系统中，提供了一种系统，包括：运动计算部分，用于 在对应于压缩目标帧的时间与对应于屏幕上的其他帧的时间之间投射物体的三维空间内的运动，以计算物体屏幕内的运动矢量; 以及压缩部，其通过基于运动矢量的运动补偿来压缩压缩对象帧。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007048052A

公开(公告)日：2007-02-22

申请号：JP2005232085

申请日：2005-08-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OBARA MORIMIKI ,  HAYATA YASUHIKO ,  INOUE HIROSHI ,  MORIYAMA TAKAO ,  KOMATSU HIDEAKI

IPC: G06F9/45

CPC classification number: G06F8/45

Abstract: PROBLEM TO BE SOLVED: To run a program efficiently in a new processor for parallel processing, such as a multi-core processor. SOLUTION: A compiler is provided, which optimizes parallel processing. The compiler records the number of execution cores being the number of processor cores for executing a target program. First, the compiler detects dominant paths being candidates for execution paths to be continuously executed by a single processor core in the target program. Next, the compiler selects the number of dominant paths which is not more than the number of execution cores to thereby generate a cluster of tasks to be parallelly or continuously executed by a multi-core processor. Then, the compiler calculates an execution time when the number of processor cores, equal to one or more natural numbers executes the generated cluster about each of the one or more natural numbers which are not greater than the number of the execution cores for each generated cluster. Then, the number of processor cores to be allocated to execute each cluster is selected on the basis of the calculated execution time. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了并行处理的新处理器，例如多核处理器，有效地运行程序。 解决方案：提供了一个优化并行处理的编译器。 编译器将执行核心数作为执行目标程序的处理器核心数量。 首先，编译器检测主路径是目标程序中的单个处理器核心连续执行的执行路径的候选。 接下来，编译器选择不大于执行核心数量的主要路径的数量，从而生成要由多核处理器并行或连续执行的任务簇。 然后，编译器计算当等于一个或多个自然数的处理器核心的数量对于每个生成的集群执行生成的集群时，关于每个生成的集群的执行核心数不大于一个或多个自然数的每一个 。 然后，根据计算出的执行时间来选择要分配用于执行每个集群的处理器核心的数量。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005157955A

公开(公告)日：2005-06-16

申请号：JP2003398823

申请日：2003-11-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： INOUE HIROSHI ,  MORIYAMA TAKAO ,  NEGISHI YASUSHI ,  OBARA MORIMIKI

IPC: G06F9/46 ,  G06F9/48 ,  G06F15/173

CPC classification number: G06F9/4887

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for increasing the throughput of a system by guaranteeing the deadline of a real-time process on a CPU that uses an SMT, while implementing as many other processes as possible concurrently, and to provide a recording medium on which a program providing the functions thereof is recorded.
SOLUTION: The system includes a measuring part 61 for measuring the computational complexity for a process obtained through a calculation process implemented by a processor 41 serving as a calculation resource; an extra time determining part 62 that causes an interrupt in the calculation process by the processor 41 to obtain the computational complexity obtained up to the time of the interrupt from the measuring part 61 and give the obtained amount of calculations to the processor 41 to calculate extra time and determine whether or not there is extra time; and a process interrupting part 63 that causes the processor 41 to interrupt the calculations of the other processes if the extra time determining part 62 determines that there is no extra time.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种系统和方法，通过保证使用SMT的CPU上的实时过程的最后期限来提高系统的吞吐量，同时尽可能多地执行其他过程， 并提供记录有提供其功能的程序的记录介质。 解决方案：该系统包括测量部件61，用于测量由作为计算资源的处理器41实现的计算处理获得的处理的计算复杂度; 额外的时间确定部分62，由处理器41在计算过程中引起中断，以从测量部分61获得直至中断时获得的计算复杂度，并将获得的计算量给予处理器41以计算额外的 时间并确定是否有额外的时间; 以及过程中断部分63，如果额外时间确定部分62确定没有额外的时间，则使得处理器41中断其他进程的计算。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH09282470A

公开(公告)日：1997-10-31

申请号：JP8356196

申请日：1996-04-05

Applicant: IBM

Inventor： ONO MAKOTO ,  TAKATSU YOSHIHISA ,  OTANI MUNETAKA ,  MORIYAMA TAKAO

IPC: G06F3/153 ,  G06T1/00 ,  G06T1/20 ,  G06T11/40 ,  G06T15/04 ,  G06T11/00 ,  G06T15/00

Abstract: PROBLEM TO BE SOLVED: To allow each node processor of a geometry subsystem to operate without considering memory resources on the side of a raster subsystem by providing a texture memory and a texture memory managing means. SOLUTION: A merge processor 30 includes a texture list 30-1 for managing the contents of a texture memory 45 being the memory resource of a raster subsystem. When texture ID designated by a texture command outputted by each geometry node processor 20 is absent, the merge processor 30 issues an interruption request to a resource managing unit 35. The resource managing unit 35 downloads texture data corresponding to texture ID designated by the request to the texture memory 45. Texture memory is downloaded without regard to geometry processing.

公开(公告)号：JPH0877385A

公开(公告)日：1996-03-22

申请号：JP20357894

申请日：1994-08-29

Applicant: IBM

Inventor： NAKAMURA HIDEFUMI ,  MORIYAMA TAKAO ,  KAWASE KATSURA

IPC: G06T9/00 ,  G06T11/20 ,  G06T15/00 ,  G06T17/10

Abstract: PURPOSE: To efficiently execute the function of texture mapping in a computer graphics interface. CONSTITUTION: In this computer graphics device 10, a texture generator 14 is connected to fragment generators 32 to 38 through a command bus 16. The generator 14 is connected to a texture data bus 20 through a texture memory cluster 22 constituted of an address generator 62 connected to a texture coordinate bus 18, a filter 66 and eight memories 64A to 64H. In addition the generator 14 is connected to the texture data bus through clusters 24 to 28. Plotting processors 42 to 48 to which frame memories 52 to 58 are connected correspondingly are connected to the bus 20. Texture mapping is executed by efficiently utilizing the texture memory cluster.