公开(公告)号：BR8500946A

公开(公告)日：1985-10-22

申请号：BR8500946

申请日：1985-03-04

Applicant: IBM

Inventor： CHESELKA HARRY ,  HLADIK GERALD JOHN ,  KARABATSOS CHRIS ,  MOSHER LAWRENCE GEDNEY ,  MORRISON RICHARD MARTIN

IPC: G06F12/02 ,  G06F13/00 ,  G06F13/12 ,  G06F13/14 ,  G06F13/38

公开(公告)号：AU3951585A

公开(公告)日：1985-09-12

申请号：AU3951585

申请日：1985-03-05

Applicant: IBM

Inventor： CHESELKA HARRY ,  KARABATSOS CHRIS ,  MORRISON RICHARD MARTIN ,  HLADIK GERALD JOHN ,  MOSHER LAWRENCE GEDNEY

IPC: G06F12/02 ,  G06F13/00 ,  G06F13/12 ,  G06F13/14 ,  G06F13/38

公开(公告)号：DE3689241T2

公开(公告)日：1994-05-11

申请号：DE3689241

申请日：1986-05-28

Applicant: IBM

Inventor： BUCKLEY JAMES FRANCIS ,  KEENEY GARRISON QUAY ,  MORRISON RICHARD MARTIN ,  STEMBER MICHAEL JOSEPH ,  WENDELL EDWARD JOSEPH

IPC: G06F9/00 ,  G06F11/22 ,  G06F12/06 ,  G06F11/00

Abstract: A terminal controller system is described wherein several feature cards are plugged into slots on a board, and I/O signal cables are connected between cards and/or remote multiplexors or terminals. A special purpose card identification (ID) bus is driven by the feature cards and received by an ID adapter. The ID adapter has one select line running to each of the slots on the board. The ID adapter enables the selected lines one at a time, whereby the selected feature cards drive their IDs onto the ID bus. A processor records the slot population by ID and also can analyse the IDs to determine if a valid configuration exists. The processor then performs a wrap test on each of its ports. This test alters the ID which it wraps and by comparison with the IDs recorded originally, this enables the processor to logically establish the physical link to particular cards connected to the ports.

公开(公告)号：DE3689241D1

公开(公告)日：1993-12-09

申请号：DE3689241

申请日：1986-05-28

Applicant: IBM

Inventor： BUCKLEY JAMES FRANCIS ,  KEENEY GARRISON QUAY ,  MORRISON RICHARD MARTIN ,  STEMBER MICHAEL JOSEPH ,  WENDELL EDWARD JOSEPH

IPC: G06F9/00 ,  G06F11/22 ,  G06F12/06 ,  G06F11/00

Abstract: A terminal controller system is described wherein several feature cards are plugged into slots on a board, and I/O signal cables are connected between cards and/or remote multiplexors or terminals. A special purpose card identification (ID) bus is driven by the feature cards and received by an ID adapter. The ID adapter has one select line running to each of the slots on the board. The ID adapter enables the selected lines one at a time, whereby the selected feature cards drive their IDs onto the ID bus. A processor records the slot population by ID and also can analyse the IDs to determine if a valid configuration exists. The processor then performs a wrap test on each of its ports. This test alters the ID which it wraps and by comparison with the IDs recorded originally, this enables the processor to logically establish the physical link to particular cards connected to the ports.