公开(公告)号：DE69405831D1

公开(公告)日：1997-10-30

申请号：DE69405831

申请日：1994-07-29

Applicant: IBM

Inventor： KOBAYASHI MASAKI ,  KATAOKA RIEKO ,  NAITOH MASAHIRO

IPC: G09G5/02 ,  G09G1/00 ,  G09G5/04 ,  G09G5/10 ,  G09G5/18 ,  H04N9/72

Abstract: A display device controller has digital RGB colour signal lines and horizontal and vertical sync signal lines (7, 8). NAND gates (9) detect in respect of at least one of the RGB colour signal lines when the digital signal on that line corresponds to a black level, and a D/A converter (10) and an adder (+) add to at least one of the horizontal and vertical sync signal lines a signal corresponding to the black level signal so detected.

公开(公告)号：DE69405831T2

公开(公告)日：1998-03-26

申请号：DE69405831

申请日：1994-07-29

Applicant: IBM

Inventor： KOBAYASHI MASAKI ,  KATAOKA RIEKO ,  NAITOH MASAHIRO

IPC: G09G5/02 ,  G09G1/00 ,  G09G5/04 ,  G09G5/10 ,  G09G5/18 ,  H04N9/72

Abstract: A display device controller has digital RGB colour signal lines and horizontal and vertical sync signal lines (7, 8). NAND gates (9) detect in respect of at least one of the RGB colour signal lines when the digital signal on that line corresponds to a black level, and a D/A converter (10) and an adder (+) add to at least one of the horizontal and vertical sync signal lines a signal corresponding to the black level signal so detected.