公开(公告)号：JP2000132507A

公开(公告)日：2000-05-12

申请号：JP30526998

申请日：1998-10-27

Applicant: IBM

Inventor： INOUE KAZUNORI ,  FUKUHISA RYOJI ,  NAKAMURA YASUHIRO ,  ISHIBASHI KAZUYUKI ,  SAITO HIROSHI

IPC: G06F13/12 ,  G06F13/42

Abstract: PROBLEM TO BE SOLVED: To provide a command processing method which is used for an SCSI (small computer system interface) protocol and can improve the system throughput and also to provide a device that can be used for the command processing method. SOLUTION: This command processing method is applied to the queuing with a tag having >=2 queue depth of an SCSI protocol. When the continuous write commands are processed, the end of each write command is detected and a response is returned to a host to notify the end of the writing. If the new commands which can be continuously processed are received against a command that is currently processed, the received new commands are added to the command under processing to dynamically extend the internal processing information. Thus, the received commands are executed continuously to the command under processing. In such a constitution, the system throughput can be improved.

公开(公告)号：JPH10214201A

公开(公告)日：1998-08-11

申请号：JP1574397

申请日：1997-01-29

Applicant: MITSUBISHI ELECTRIC CORP ,  MITSUBISHI DENKI SYS LSI DES ,  IBM

Inventor： ITO SAKAE ,  KANZAKI TERUAKI ,  AKATSUKI TADAYUKI ,  SAKAI TATSUYA ,  NUMATA TSUTOMU ,  NAKAMURA YASUHIRO

IPC: G06F11/28 ,  G06F9/06 ,  G06F11/36 ,  G06F15/78

Abstract: PROBLEM TO BE SOLVED: To obtain a microcomputer in which a debug circuit equipped with various functions used at the time of program debugging is provided in the microcomputer, and a flash memory electrically capable of writing/erasing incorporated on the same chip can be used as an emulation memory. SOLUTION: This device is provided with a flash memory 6 electrically capable of writing/erasing in which a program in a development stage is stored and a debug circuit 7 having an exclusive input and output terminal 8 for connection with an outside ICE are incorporated in this device. The debug circuit 7 is provided with a communicating function with a CPU 1, a communicating function with the ICE, the trace function of the operating state of the CPU 1, break function for generating debug interruption, function for writing a program code from the ICE in the flash memory 6, and function for transmitting the content of the flash memory 6 to the ICE.