公开(公告)号：DE3177245D1

公开(公告)日：1991-07-11

申请号：DE3177245

申请日：1981-08-10

Applicant: IBM

Inventor： AICHELMANN JR ,  NEVES FERNANDO

IPC: G11C19/00 ,  G11C19/28 ,  G11C27/04

Abstract: A recirculating loop memory array is adapted for the parallel as well as serial fetching and storing of data while requiring only a single input and single output data terminal. Each (1, 2...N) of the array is provided with a shift register stage (1', 2'...N') for parallel data accessing. A particular recirculating bit in all of the loops can be fetched in parallel into their respective shift register stages and, conversely, the bits stored in the shift register stages can be loaded in parallel into predetermined recirculating bits of their respective loops. The shift register (7) is operated at high speed so that it may be completely loaded or unloaded during the interval between successive steppings of the loops.