公开(公告)号：JP2000174025A

公开(公告)日：2000-06-23

申请号：JP29247099

申请日：1999-10-14

Applicant: IBM

Inventor： SAIPUREIN E UZOO ,  STEPHEN H BETCHER ,  PATRICK W DEHABAAN ,  PARKS CHRISTOPHER C ,  SIMON ANDREW H

IPC: H01L21/3205 ,  C25D5/10 ,  C25D7/00 ,  C25D7/12 ,  H01L21/288 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a high concn. impurity content and a resistance to the crystal grain growth by keeping a substrate in a plating soln. after electrodepositing a Cu-contg. film on a seed layer of the substrate dipped in the plating soln., electrodepositing a Cu-contg. film, and removing and drying the substrate from the plating soln. SOLUTION: A first electrodeposited metal film layer 22 is formed on an exposed region of the top of a metal seed layer 6, an impurity film 26 is laminated on a fine structure contg. a rough surface 24' of the metal film layer 22, this film 26 has a top surface and is composed of a heavy dopant from an electroplating soln., an electrodeposited metal film layer 30 is formed on the impurity film 26. This film 26 gives a heavily doped region which is integrated with a rough surface 24' to give a nature of suppressing the crystal grain growth and the electromigration resistance to composite metal conductive wires 39. Thus it is possible to obtain a superior electric, thermodynamic and metallurgical nature.

公开(公告)号：JP2000183302A

公开(公告)日：2000-06-30

申请号：JP35805299

申请日：1999-12-16

Applicant: IBM ,  SIEMENS AG

Inventor： SUSAN E SHARUU ,  TSUE CHIAN CHEN ,  JONATHAN E FALTERMAIER ,  GRUENING ULRIKE ,  RAJARAAO JANMII ,  MANDELMAN JACK A ,  PARKS CHRISTOPHER C ,  PAUL C PARIIZU ,  PAUL A RONSUHAIMU ,  YUN YUU WAN

IPC: B82B1/00 ,  H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain a trench capacitor structure in which mutual influence can be reduced between the regions whose crystallization levels are different. SOLUTION: In a trench capacitor 40, a substrate 60 is provided with a trench 44, an embedded plate electrode 42, a node dielectric 46, an oxide collars 48, trench electrode materials 50, and a conductive type strap 56. A quantum conductive layer which is a silicon nitride thin film is arranged on a boundary face 58 between the conductive strap 56 and the substrate 60 and a boundary face 62 between the trench electrode 50 and the conductive strap 56. The transmission of the recrystallizing force of the trench electrode 50 and the strap 56 to the strap 56 or the substrate 60 can be reduced by this quantum conductive layer. Thus, the reliability of the device can be improved.

公开(公告)号：JPH11163160A

公开(公告)日：1999-06-18

申请号：JP27147398

申请日：1998-09-25

Applicant: SIEMENS AG ,  IBM

Inventor： LOH STEPHEN K ,  DEHM CHRISTINE ,  PARKS CHRISTOPHER C

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To reduce the diffusion effects of a dopant in a gate structure, without compromising the completeness or characteristics of an integrated circuit, including the gate structure by forming a laminar Si structure on a gate oxide layer formed on a substrate. SOLUTION: A gate structure is formed on a substrate 206 with a gate oxide layer 208 formed on the substrate 206. An Si layer 210 is formed on the gate oxide layer 208 and doped, utilizing a dopant. A barreir layer on the Si layer 210 is disposed at the grain boundary of this layer 210 to reduce the dopant diffusing out vertically or sideward from the Si layer 210 during an annealing process associated with forming sources or drains, utilizing the gate structure 204. As a result, controls the diffusion of the dopant is controlled and a low contact resistance and completeness are maintained.

公开(公告)号：DE69836607T2

公开(公告)日：2007-10-11

申请号：DE69836607

申请日：1998-09-01

Applicant: QIMONDA AG ,  IBM

Inventor： LOH STEPHEN K ,  PARKS CHRISTOPHER C ,  DEHM CHRISTINE

IPC: H01L21/28 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/49

Abstract: Methods and apparatus for to methods and apparatus for fabricating gate structures, which include barrier layers, within an integrated circuit are disclosed. According to one aspect of the present invention, a method for minimizing dopant outdiffusion within an integrated circuit involves forming a gate oxide 208 layer over a substrate 206, and forming a layered silicon structure 210 over the gate oxide layer. A silicide layer 214 is formed atop the layered silicon structure. In one embodiment, forming a layered silicon structure includes depositing a first doped silicon layer over the gate oxide layer, forming a first oxide layer over the first silicon layer, nitridizing the first oxide layer, and etching the nitridized first oxide layer to expose nitride at a grain boundaries of the first silicon layer. A second silicon layer may then be deposited over the nitride exposed at the grain boundaries of the first silicon layer. In such an embodiment, nitridizing the first oxide layer causes nitrogen to be diffused into at least a portion of the first doped silicon layer.

公开(公告)号：DE69836607D1

公开(公告)日：2007-01-25

申请号：DE69836607

申请日：1998-09-01

Applicant: QIMONDA AG ,  IBM

Inventor： LOH STEPHEN K ,  PARKS CHRISTOPHER C ,  DEHM CHRISTINE

IPC: H01L21/28 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/49

Abstract: Methods and apparatus for to methods and apparatus for fabricating gate structures, which include barrier layers, within an integrated circuit are disclosed. According to one aspect of the present invention, a method for minimizing dopant outdiffusion within an integrated circuit involves forming a gate oxide 208 layer over a substrate 206, and forming a layered silicon structure 210 over the gate oxide layer. A silicide layer 214 is formed atop the layered silicon structure. In one embodiment, forming a layered silicon structure includes depositing a first doped silicon layer over the gate oxide layer, forming a first oxide layer over the first silicon layer, nitridizing the first oxide layer, and etching the nitridized first oxide layer to expose nitride at a grain boundaries of the first silicon layer. A second silicon layer may then be deposited over the nitride exposed at the grain boundaries of the first silicon layer. In such an embodiment, nitridizing the first oxide layer causes nitrogen to be diffused into at least a portion of the first doped silicon layer.