1.
    发明专利
    未知

    公开(公告)号:DE2847960A1

    公开(公告)日:1979-05-31

    申请号:DE2847960

    申请日:1978-11-04

    Applicant: IBM

    Abstract: The disclosed embodiments filter out many unnecessary interrogations of the cache directories of processors in a multiprocessor (MP) system, thereby reducing the required size of the buffer invalidation address stack (BIAS) with each associated processor, and increasing the efficiency of each processor by allowing it to access its cache during the machine cycles which in prior MP's had been required for invalidation interrogation. Invalidation interrogation of each remote processor cache directory may be done when each channel or processor generates a store request to a shared main storage.

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